Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf
X86: Fix immediate type of FOO64i32 operations.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:35 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
...
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
...
16-bit and 32-bit pushf and popf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 15:42:55 +00:00
Dan Gohman
7f357ec6d2
Add mayLoad and mayStore flags to instructions which missed them.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:34:55 +00:00
Chris Lattner
e1611f26e3
fix rdar://7947167 - llvm-mc doesn't match movsq
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
...
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Kevin Enderby
a0161cd6f8
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
...
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:42:46 +00:00
Kevin Enderby
eb612347f4
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
...
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:03:31 +00:00
Dan Gohman
71edb241a1
Remove the -disable-16bit command-line option, which is now obsolete.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 18:30:26 +00:00
Evan Cheng
2bce5f4b56
Enable i16 to i32 promotion by default.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
Evan Cheng
8b1190a540
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:18:01 +00:00
Chris Lattner
d486d77444
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest
...
nodes all have an EFLAGS result when made by isel lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:07:17 +00:00
Chris Lattner
baba4bb72f
eliminate the last of the parallel's!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99700 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 02:47:14 +00:00
Chris Lattner
7e504141e0
remove 64-bit or_is_add parallels.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:16:52 +00:00
Chris Lattner
99521af212
remove the patterns that I commented out in r98930, Dan verified
...
that they are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:43:36 +00:00
Daniel Dunbar
0180daee02
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 18:07:48 +00:00
Chris Lattner
1d7dbd1716
comment out a bunch of parallel store patterns that apparently
...
can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:14:21 +00:00
Daniel Dunbar
c28c7689fc
X86: Fix encoding for TEST64rr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:15:03 +00:00
Chris Lattner
e3486a4c9a
Now that tblgen can handle matching implicit defs of instructions
...
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
Chris Lattner
e10038e54e
callq is pcrelative
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 17:52:22 +00:00
Chris Lattner
4d82068167
fix the same bug on the x86-64 side of the fence.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98616 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 06:39:08 +00:00
Evan Cheng
700c71d2e8
Fix jit encoding bugs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 19:28:34 +00:00
Evan Cheng
f48ef03655
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 03:48:46 +00:00
Daniel Dunbar
bf2d4c034d
X86_64: Fix encoding for the rest of the 64i32 instructions too.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:57:53 +00:00
Daniel Dunbar
859c9dc867
X86: Fix ADD64i32 encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:49:39 +00:00
Daniel Dunbar
96e2cec9c7
MC/X86_64: Fix matching of leaq.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:44 +00:00
Daniel Dunbar
989ac72981
MC/X86_64: Fix matching of callq.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:38 +00:00
Chris Lattner
341b27406d
Correct immediate sizes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 18:55:15 +00:00
Chris Lattner
1840991d54
factor the 'sign extended from 8 bit' patterns better so
...
that they are not destination type specific. This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 01:45:01 +00:00
Dan Gohman
bc9d98b52d
The mayHaveSideEffects flag is no longer used.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 23:47:46 +00:00
Chris Lattner
4446c3f4d0
fix an incorrect (overly conservative) predicate.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27 08:18:55 +00:00
Chris Lattner
6d9f86b773
remove a bunch of dead named arguments in input patterns,
...
though some look dubious afaict, these are all ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 06:54:29 +00:00
Chris Lattner
be5ad7dce2
fix a type mismatch in this pattern, where we were using an i64 imm in a
...
place where an i32 imm was required, the old isel just got lucky.
This fixes CodeGen/X86/x86-64-and-mask.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-23 06:09:57 +00:00
Chris Lattner
a599de2410
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
...
fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
Daniel Dunbar
ccfa1db538
X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented
...
with "tied memory operands", which is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:22:03 +00:00
Chris Lattner
518bb53485
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 19:54:29 +00:00
Chris Lattner
be1778fea7
really kill off the last MRMInitReg inst, remove logic from encoder.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-05 21:34:18 +00:00
Chris Lattner
c74e333ecc
factor code better in X86MCInstLower::Lower, teach it to
...
lower the SETB* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-05 21:13:48 +00:00
Evan Cheng
aa92bec010
Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-31 07:28:44 +00:00
Daniel Dunbar
8a3ee718cd
Mark EH_RETURN64 as CodeGenOnly.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 20:16:37 +00:00
Evan Cheng
3bda20112e
Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 18:31:19 +00:00
Dan Gohman
f1b4d26e67
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12 04:42:54 +00:00
Evan Cheng
199c4240fe
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 22:03:29 +00:00
Evan Cheng
05920b8146
Revert 93158. It's breaking quite a few x86_64 tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 21:13:41 +00:00
Dan Gohman
e5dacc55ad
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
...
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.
FileCheckize, tidy, and extend a testcase to cover this case.
This fixes rdar://7527390.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11 17:58:34 +00:00