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17707 Commits

Author SHA1 Message Date
David Greene
c38a03eeca [AVX] VEXTRACTF128 support. This commit includes patterns for 
matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values.  VINSERTF128 comes next.  With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-03 15:50:00 +00:00
Richard Osborne
17c1e51d22 Add XCore intrinsics for resource instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-03 13:14:25 +00:00
Rafael Espindola
f297c93191 Fix PR9127 by reversing the operands even if they have more then one use. 
Reversing the operands allows us to fold, but doesn't force us to. Also, at
this point the DAG is still being optimized, so the check for hasOneUse is not
very precise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-03 03:58:05 +00:00
Bob Wilson
92e7195e43 Update comment to match my recent change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124725 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-02 17:29:40 +00:00
Benjamin Kramer
56442dfdcf SimplifyCFG: Turn switches into sub+icmp+branch if possible. 
This makes the job of the later optzn passes easier, allowing the vast amount of
icmp transforms to chew on it.

We transform 840 switches in gcc.c, leading to a 16k byte shrink of the resulting
binary on i386-linux.

The testcase from README.txt now compiles into
  decl  %edi
  cmpl  $3, %edi
  sbbl  %eax, %eax
  andl  $1, %eax
  ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-02 15:56:22 +00:00
Richard Osborne
ff0c5014b2 Add support for trampolines on the XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-02 14:57:41 +00:00
Sean Callanan
1e1901a294 Fixed a bug in the disassembler where the mandatory 0x66 
prefix would be misinterpreted in some cases on 32-bit
x86 platforms.  Thanks to Olivier Meurant for identifying
the bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-02 01:09:02 +00:00
Evan Cheng
31959b19a7 Given a pair of floating point load and store, if there are no other uses of 
the load, then it may be legal to transform the load and store to integer
load and store of the same width.

This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []

to

ldr r12, []
str r12, []

rdar://8944252


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-02 01:06:55 +00:00
Bob Wilson
692df93de4 PR9081: Split up LDM instruction with deprecated use of both LR and PC. 
This is completely untested but pretty straightforward, so hopefully I
got it right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124694 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 22:30:51 +00:00
Anton Korobeynikov
cf2cdc9cae Fix imm printing for logical instructions. 
Patch by Brian G. Lucas!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124679 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 20:22:53 +00:00
Carl Norum
e47023d543 Test commit - fix a double 'should' in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 07:38:42 +00:00
Evan Cheng
2bffee2ee7 Patches to build EFI with Clang/LLVM. By Carl Norum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-01 01:14:13 +00:00
Devang Patel
e9a7ea6865 Keep track of incoming argument's location while emitting LiveIns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-31 21:38:14 +00:00
David Greene
9f08f60993 Fix vector sign extend to put the source and destination types in the 
correct places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124601 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-31 20:39:01 +00:00
Chris Lattner
fd2ad8783c add a note, progress unblocked by PR8575 being fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-31 20:23:28 +00:00
Anton Korobeynikov
98b928ea71 Save a mapping between original and cloned constpool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-30 22:07:39 +00:00
Benjamin Kramer
9b108a338d Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off. 
This happens all the time when a smul is promoted to a larger type.

On x86-64 we now compile "int test(int x) { return x/10; }" into
  movslq  %edi, %rax
  imulq $1717986919, %rax, %rax
  movq  %rax, %rcx
  shrq  $63, %rcx
  sarq  $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax"
  addl  %ecx, %eax

This fires 96 times in gcc.c on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-30 16:38:43 +00:00
Bob Wilson
d11c57a937 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-28 17:50:30 +00:00
Evan Cheng
c3a20bab75 Fix PLD encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:48:34 +00:00
Kevin Enderby
9e56fb12c5 Changed llvm-mc arm target to give an error if .syntax divided is used. Since 
only .syntax unified is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 23:22:36 +00:00
David Greene
54d8ebafc7 [AVX] Clean up the code to configure target lowering for AVX. Specify 
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124447 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 22:38:56 +00:00
Roman Divacky
bf7553210a Introduce virtual ParseRegister method in TargetAsmParser. 
Create override of this method in X86/ARM/MBlaze.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 17:14:22 +00:00
Eric Christopher
4a2b316762 Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124357 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 05:44:56 +00:00
NAKAMURA Takumi
40ccb798cc lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64. 
CALL64 marks %xmm* as dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-27 03:20:19 +00:00
Bill Wendling
8cb415e4c0 Add support for printing out floating point values from the ARM assembly 
parser. The parser will always give us a binary representation of the floating
point number.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 20:57:43 +00:00
David Greene
cfe33c46aa [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a 
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 19:13:22 +00:00
David Greene
91585098ef [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default 
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 15:38:49 +00:00
Bruno Cardoso Lopes
1b10d5be40 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 13:28:14 +00:00
Bill Wendling
717082b9bd Add needed braces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124273 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:06:22 +00:00
NAKAMURA Takumi
7754f85885 Target/X86: Tweak win64's tailcall. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:04:09 +00:00
NAKAMURA Takumi
e5fffe9c3f Fix whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 02:03:37 +00:00
NAKAMURA Takumi
c5b7a4223d lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 01:28:06 +00:00
NAKAMURA Takumi
b901076387 lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-26 01:27:58 +00:00
Bill Wendling
0f4db7efa1 Revert 124230. It was causing test failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:48:36 +00:00
Bill Wendling
261b9c1a35 The floating point value is encoded in its binary form as an Imm. Convert it 
appropriately so that it prints out the decimal representation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 21:27:46 +00:00
Evan Cheng
7cfa656ad8 Don't merge restore with tail call instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-25 01:28:33 +00:00
Anton Korobeynikov
5899a60d2f Provide correct registers for EH stuff on ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 22:38:45 +00:00
Chris Lattner
ccea167db5 fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 03:42:46 +00:00
Chris Lattner
96c0771c01 this isn't a memset, we do convert dest[i] to one though :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 02:32:00 +00:00
Chris Lattner
7ea7d32de6 with recent work, we now optimize this into: 
define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-24 01:12:18 +00:00
Anders Carlsson
f330b3227a Add a memset loop that LoopIdiomRecognize doesn't recognize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 20:31:00 +00:00
Rafael Espindola
dd0dfdf8be Initialize MCNoExecStack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 18:50:12 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:55:27 +00:00
Ted Kremenek
584520e8e2 Null initialize a few variables flagged by 
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 17:05:06 +00:00
Rafael Espindola
0cf5e3d51d Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 05:43:40 +00:00
Rafael Espindola
1c13026e8f Remove more duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:43:11 +00:00
Rafael Espindola
c85dca66e6 Remove duplicated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-23 04:28:49 +00:00
Venkatraman Govindaraju
8184e289db Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-22 13:05:16 +00:00
Venkatraman Govindaraju
e105a3901f Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju
fc3faa75cb Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-01-21 22:00:00 +00:00