6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-01 04:29:57 +00:00
Code Issues Projects Releases Wiki Activity
42,351 Commits 39 Branches 0 Tags 277 MiB
97f48c39fd
Commit Graph

9806 Commits

Author SHA1 Message Date
Evan Cheng
97f48c39fd Encode extend instructions; more clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 22:15:19 +00:00
Evan Cheng
12c3a533c5 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 17:48:05 +00:00
Evan Cheng
d87293ce78 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 08:47:38 +00:00
Mon P Wang
f007a8b931 Widening cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58796 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 05:31:54 +00:00
Evan Cheng
eb4f52eb62 Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 03:35:07 +00:00
Evan Cheng
9092213a5e Fix so_imm encoding bug; add support for MOVi2pieces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58790 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 02:25:39 +00:00
Evan Cheng
fbc9d412ef Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-06 01:21:28 +00:00
Evan Cheng
83b5cf0272 Encode pic load / store instructions; fix some encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 23:22:34 +00:00
Evan Cheng
edda31c412 Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 18:35:52 +00:00
Dan Gohman
cbb7ab259d Reintroduce a comment that was removed with the AddToISelQueue 
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58760 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 17:16:24 +00:00
Richard Osborne
617303ac71 Test commit, add Makefile for XCore target, more to follow. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 09:53:58 +00:00
Evan Cheng
b35ed9247a Add more vector move low and zero-extend patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58752 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 06:04:51 +00:00
Evan Cheng
9dd93b36b8 Indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58750 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 06:03:38 +00:00
Dan Gohman
8be6bbe5bf Eliminate the ISel priority queue, which used the topological order for a 
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 04:14:16 +00:00
Dan Gohman
fa210d8dd1 Use getTargetConstant instead of getConstant for nodes that should not be visited 
by isel and potentially forced into registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58747 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 02:06:09 +00:00
Evan Cheng
c96a8e7df1 Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS X 
indirect gv reference. Please don't call it lazy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-05 01:50:32 +00:00
Evan Cheng
3eb22e835f Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 22:19:55 +00:00
Evan Cheng
c7c77297e2 Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 19:57:48 +00:00
Evan Cheng
142c15e052 Debug output tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58708 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 17:58:53 +00:00
Evan Cheng
e7fe672445 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 17:57:07 +00:00
Evan Cheng
b0b53491ef For some targets, it's not possible to place GVs in the same memory buffer as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements. 
This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 09:30:48 +00:00
Evan Cheng
e953b89b0d Stylistic change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58683 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 06:10:06 +00:00
Evan Cheng
25e04788bf Handle ARM machine constantpool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58671 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-04 00:50:32 +00:00
Dan Gohman
f6503a031e The ANDMask node folds to a constant, and isn't the node that needs to 
have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58655 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 23:43:55 +00:00
Evan Cheng
49987360ad Remove a dead switch statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58644 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 21:26:52 +00:00
Evan Cheng
afaf12036d Minor code restructuring. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58643 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 21:02:39 +00:00
Jim Grosbach
0a4b9dc9b1 Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 18:38:31 +00:00
Dan Gohman
8f092252d3 Refactor various TargetAsmInfo subclasses' TargetMachine members away 
adding a TargetMachine member to the base TargetAsmInfo class instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-03 18:22:42 +00:00
Bill Wendling
7ab1fc1490 Whitespace fixes. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58539 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 21:26:08 +00:00
Evan Cheng
2583b2a713 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58533 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:56:03 +00:00
Evan Cheng
938b9d8ef7 Use better data structure for ConstPoolId2AddrMap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58532 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:55:13 +00:00
Evan Cheng
ba44df60d6 Actually make debug output understandable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58529 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:15:52 +00:00
Mon P Wang
fd532d7cd9 x86_64 rip-relative and magic mode address 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58528 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:13:42 +00:00
Evan Cheng
c072966838 Forgot this in last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58527 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:11:09 +00:00
Evan Cheng
eb4ed4b266 Encode PICADD; some code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58526 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 19:10:44 +00:00
Bill Wendling
f7c094000f Revert r58489. It isn't correct for all cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58523 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 18:30:19 +00:00
Evan Cheng
9ed08f4a41 Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 16:52:57 +00:00
Bill Wendling
f6a9988cea Don't skip over all "terminator" instructions when determining where to put the 
callee-saved restore code. It could skip over conditional jumps
accidentally. Instead, just skip the "return" instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58489 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 04:00:23 +00:00
Dan Gohman
d17cfbe1ca Use MOVSSmr instead of EXTRACTPSmr in the case of extracting 
vector element 0 for a store, as it's smaller and faster.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58483 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-31 00:57:24 +00:00
Evan Cheng
e53a5af966 I think we got non-machine specific constpool entries covered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58474 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 23:43:36 +00:00
Duncan Sands
2fbfbd2a05 Shift amounts should have type getShiftAmountTy 
(i32 for PPC, not i8).  Correct this, and some
formatting while there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58451 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 19:28:32 +00:00
Duncan Sands
fa7935fcb3 Shift amounts should have the type given by 
getShiftAmountTy (i32 in the case of CellSPU).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58449 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 19:24:28 +00:00
Evan Cheng
65f244261c ARM JIT should observe -relocation-model command line option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58433 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 16:10:54 +00:00
Mon P Wang
0c39719bfc Add initial support for vector widening. Logic is set to widen for X86. 
One will only see an effect if legalizetype is not active.  Will move
support to LegalizeType soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 08:01:45 +00:00
Scott Michel
d976c21241 Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stack 
so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU.

N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is
still unexorcised code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58415 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-30 01:51:48 +00:00
Evan Cheng
0f282439be Correct way to handle CONSTPOOL_ENTRY instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58409 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-29 23:55:43 +00:00
Evan Cheng
5be59eace5 Add debugging support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58408 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-29 23:55:17 +00:00
Nate Begeman
110e3b3d1b Fix PEXTRQ encoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58403 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-29 23:07:17 +00:00
Dale Johannesen
b384ab9ea1 Add a RM pseudoreg for the rounding mode, which 
allows ppcf128->int conversion to work with
DeadInstructionElimination.  This is now turned
off but RM is harmless.  It does not do a complete
job of modeling the rounding mode.

Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now.  Eventually it should go back in and the
other problems fixed where they're broken.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-29 18:26:45 +00:00
Jim Grosbach
bc6d876adf Support for constant islands in the ARM JIT. 
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the 
instruction stream.

Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.

For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-28 18:25:49 +00:00