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114 Commits

Author SHA1 Message Date
Chris Lattner
9b3bd467d0 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-21 20:51:05 +00:00
Chris Lattner
39afef3150 Add a build_vector node 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 06:18:01 +00:00
Chris Lattner
a064d28843 rename these nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 01:13:28 +00:00
Evan Cheng
df57fa0c7d Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26833 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 20:31:41 +00:00
Chris Lattner
89fad2c3b2 Disable x86 fastcc from passing args in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26824 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 17:27:47 +00:00
Chris Lattner
1c636e9d98 Parameterize the number of integer arguments to pass in registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26818 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 05:10:20 +00:00
Nate Begeman
81e8097377 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-17 01:40:33 +00:00
Evan Cheng
2221de9cc1 Bug fix: condition inverted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26804 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 22:02:48 +00:00
Evan Cheng
714554d707 Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-16 21:47:42 +00:00
Evan Cheng
30b37b5f29 Add LSR hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26740 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:18:16 +00:00
Evan Cheng
ff909926e2 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest. 
and variable value.
Similarly for memcpy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26603 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 23:29:39 +00:00
Evan Cheng
3c992d291b Enable Dwarf debugging info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26581 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-07 02:02:57 +00:00
Chris Lattner
9601a86a64 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26541 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 05:08:37 +00:00
Evan Cheng
62bec2ca4c MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of 
rep/stos and rep/mov if the count is not a constant. We could do
  rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.

Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26517 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 02:48:56 +00:00
Evan Cheng
8df346b4e8 Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26512 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-04 01:12:00 +00:00
Chris Lattner
41edaa0529 remove the read/write port/io intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-03 00:19:58 +00:00
Evan Cheng
d30bf01e90 Vector op lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:11:20 +00:00
Evan Cheng
bbbb2fbbde Added a common about the need for X86ISD::Wrapper. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:55:19 +00:00
Evan Cheng
020d2e8e7a - Clean up the lowering and selection code of ConstantPool, GlobalAddress, 
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 20:41:18 +00:00
Evan Cheng
a0ea0539e3 PIC related bug fixes. 
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 02:43:52 +00:00
Evan Cheng
4c1aa86657 - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 20:19:42 +00:00
Evan Cheng
470a6adc78 Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 02:26:30 +00:00
Chris Lattner
1efa40f6a4 split register class handling from explicit physreg handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-22 00:56:39 +00:00
Chris Lattner
4217ca8dc1 Updates to match change of getRegForInlineAsmConstraint prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-21 23:11:00 +00:00
Evan Cheng
45af8fd8c2 If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take 
advantage of fisttpll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 07:26:17 +00:00
Evan Cheng
7ccced634a x86 / Darwin PIC support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:15:05 +00:00
Chris Lattner
c2fe97e726 unbreak the build 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 07:09:27 +00:00
Evan Cheng
5298bcc722 Unbreak x86 be 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 07:01:52 +00:00
Nate Begeman
551bf3f800 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 05:43:56 +00:00
Nate Begeman
4c5dcf54ff Kill the x86 pattern isel. boom. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-17 00:03:04 +00:00
Nate Begeman
368e18d56a Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 21:11:51 +00:00
Evan Cheng
18a8452f3d A bit more memset / memcpy optimization. 
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 00:21:07 +00:00
Evan Cheng
a03a5dc7ce Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:38:30 +00:00
Evan Cheng
87ed716d21 Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and 
maxStoresPerMemMove. Although the last one is not used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26172 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:25:08 +00:00
Chris Lattner
94dd29216c Switch targets over to using SelectionDAG::getCALLSEQ_START to create 
CALLSEQ_START nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26143 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 09:00:43 +00:00
Evan Cheng
2338c5cb0e Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete. 
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26038 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-07 08:38:37 +00:00
Evan Cheng
e3de85b447 Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a 
flag so it can be flagged to a FST.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25953 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:20:30 +00:00
Evan Cheng
d25e9e8294 Fix a erroneous comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25894 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 00:28:23 +00:00
Nate Begeman
750ac1bdfa Fix some of the stuff in the PPC README file, and clean up legalization 
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25875 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 07:19:44 +00:00
Evan Cheng
760df29881 Return's chain should be matching either the chain produced by the 
value or the chain going into the load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 01:19:32 +00:00
Evan Cheng
0d084c9e4a When folding a load into a return of SSE value, check the chain to 
ensure the memory location has not been clobbered.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25861 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 00:20:21 +00:00
Evan Cheng
0e8671bf4a Be smarter about whether to store the SSE return value in memory. If 
it is already available in memory, do a fld directly from there.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25859 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 23:19:54 +00:00
Evan Cheng
223547ab31 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25857 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 22:28:30 +00:00
Chris Lattner
259e97cc72 * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 19:43:35 +00:00
Evan Cheng
ef6ffb17c7 Added custom lowering of fabs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25831 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 03:14:29 +00:00
Evan Cheng
6dfa999c01 Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip 
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25824 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 23:41:35 +00:00
Evan Cheng
02568ff48d i64 -> f32, f32 -> i64 and some clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25818 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 22:13:22 +00:00
Evan Cheng
6dab05363f Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25817 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 08:02:57 +00:00
Chris Lattner
c6fd6cd65c Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25803 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 04:09:27 +00:00
Chris Lattner
87c890a9c2 adjust prototype 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25798 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-30 03:49:07 +00:00