Commit Graph

91660 Commits

Author SHA1 Message Date
Adrian Prantl
9d5d58a49b fix a typo that due to cu&paste quadrupled itself
rdar://problem/13056109

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 18:10:50 +00:00
Quentin Colombet
1ad3a410be ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.

Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.

This commit adds a proper diagnostic message for Imm0_4 and updates all tests.

Patch by Mihail Popa <Mihail.Popa@arm.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 17:54:54 +00:00
Rafael Espindola
140536b936 Add missing ':'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180616 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 17:54:46 +00:00
Adrian Prantl
163da93023 Bugfix for the debug intrinsic handling in InstCombiner:
Since we can't guarantee that the original dbg.declare instrinsic
is removed by LowerDbgDeclare(), we need to make sure that we are
not inserting the same dbg.value intrinsic over and over.
This removes tons of redundant DIEs when compiling optimized code.

rdar://problem/13056109

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 17:48:33 +00:00
Ulrich Weigand
a3acc2b6cf PowerPC: Use RegisterOperand instead of RegisterClass operands
In the default PowerPC assembler syntax, registers are specified simply
by number, so they cannot be distinguished from immediate values (without
looking at the opcode).  This means that the default operand matching logic
for the asm parser does not work, and we need to specify custom matchers.
Since those can only be specified with RegisterOperand classes and not
directly on the RegisterClass, all instructions patterns used by the asm
parser need to use a RegisterOperand (instead of a RegisterClass) for
all their register operands.

This patch adds one RegisterOperand for each RegisterClass, using the
same name as the class, just in lower case, and updates all instruction
patterns to use RegisterOperand instead of RegisterClass operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 16:53:15 +00:00
Silviu Baranga
730a570c8c Re-write the address propagation code for pre-indexed loads/stores to take into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:52:24 +00:00
Ulrich Weigand
069a4a9583 PowerPC: Fix encoding of vsubcuw and vsum4sbs instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes).

Tests will be added together with the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:39:57 +00:00
Ulrich Weigand
0c0a1be9c5 PowerPC: Fix encoding of stfsu and stfdu instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes).  Note that apparently
the compiler currently never generates pre-inc instructions
for floating point types for some reason ...

Tests will be added together with the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:39:40 +00:00
Ulrich Weigand
1adc97c901 PowerPC: Fix encoding of rldimi and rldcl instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).

Tests will be added together with the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:39:12 +00:00
Ulrich Weigand
8ade909308 PowerPC: Support PC-relative fixup_ppc_brcond14.
When testing the asm parser, I ran into an error when using a conditional
branch to an external symbol (this doesn't occur in compiler-generated
code) due to missing support in PPCELFObjectWriter::getRelocTypeInner.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180605 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:38:30 +00:00
Benjamin Kramer
4e8590c45d ARM/NEON: Pattern match vector integer abs to vabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 15:00:57 +00:00
Benjamin Kramer
753981784f X86: Now that we have a canonical form for vector integer abs, match it into pabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 12:05:21 +00:00
Benjamin Kramer
6242fda42a DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars.
This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180597 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 09:19:19 +00:00
Nadav Rotem
7557e521e5 LoopVectorizer: Calculate the number of pointers to disambiguate at runtime based on the numbers of reads and writes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 05:08:59 +00:00
Michael Gottesman
276b8549ee Use 'git svn find-rev' in git-svnrevert instead of shell script fu.
Thanks Chandler!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 03:27:39 +00:00
Michael Gottesman
d15d29e7c8 Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that were once autoreleaseRV instructions."
This reverts commit r180222.

I think this might tie in with a different problem which will require a
different approach potentially. I am reverting this in the case I need to go
down that second path.

My apologies for the noise. = /.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 01:12:18 +00:00
Michael Gottesman
e1f079064a Updated GettingStarted.rst so that it references utils/git-svn for git-svnup instead of catting it into the documentation itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 01:04:45 +00:00
Michael Gottesman
19c3735262 Added the scripts git-svnup/git-svnrevert to utils/git-svn.
It makes more sense to have git-svnup here than catting said file in the
documentation (where we should rather point users to this directory).
I included git-svnrevert as an additional gift to the community. I will update
the documentation in a second commit later today.

git-svnrevert takes in a git hash for a commit, looks up the svn revision for
said commit and then creates the normal git revert commit message with the one
liner message, except instead of saying

  Revert "<<<INSERT ONELINER HERE>>>"

  This reverts commit <<<INSERT GITHASH HERE>>>

It says:

  Revert "<<<INSERT ONELINER HERE>>>"

  This reverts commit r<<<INSERT SVN REVISION HERE>>>

so git hashes will not escape into our svn logs (which just look unseemly).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 00:58:45 +00:00
Jack Carter
97265a4889 Mips assembler: .set reorder support
Mips have delayslots for certain instructions 
like jumps and branches. These are instructions 
that follow the branch or jump and are executed
before the jump or branch is completed.

Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.

The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.

For backwards compatibility we need to support
.set reorder and have it be the default behavior in the 
assembler.

Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 23:31:35 +00:00
Michael Liao
0fc7137f2f Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.
Pattern has source location by itself. After adding a trivial method to
retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns.
One thing revised after this is the diagnostic info is more accurate by
pointing to the start of the CHECK-NOT pattern instead of the end of the
CHECK-NOT pattern. E.g. diagnostic message previously looks like

    <stdin>:1:1: error: CHECK-NOT: string occurred!
    test
    ^
    test.txt:1:16: note: CHECK-NOT: pattern specified here
    CHECK-NOT: test
                   ^

is changed to

    <stdin>:1:1: error: CHECK-NOT: string occurred!
    test
    ^
    test.txt:1:12: note: CHECK-NOT: pattern specified here
    CHECK-NOT: test
               ^



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 21:31:34 +00:00
Preston Gurd
7f8300b8f3 Make function documentation conform to llvm standards.
Expunge all remaining traces and use of live variable information.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180577 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 21:31:33 +00:00
Arnold Schwaighofer
45c9e0b412 ARM cost model: Integer div and rem is lowered to a function call
Reflect this in the cost model. I observed this in MiBench/consumer-lame.

radar://13354716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 21:16:18 +00:00
Andrew Kaylor
1c489455ea Re-enabling MCJIT object caching with memory leak fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 21:02:36 +00:00
Chris Lattner
29fce9ad39 revert r179735, it has no testcases, and doesn't really make sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 20:34:16 +00:00
Preston Gurd
d6ac8e9a03 This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 20:29:37 +00:00
Nadav Rotem
975b1ddf60 LoopVectorizer: No need to generate pointer disambiguation checks between readonly pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:55:03 +00:00
Reid Kleckner
4b55815303 [mc-coff] Forward Linker Option flags into the .drectve section
Summary:
This is modelled on the Mach-O linker options implementation and should
support a Clang implementation of #pragma comment(lib/linker).

Reviewers: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:34:41 +00:00
Rafael Espindola
93d0b06e2a Fix section relocation for SECTIONREL32 with immediate offset.
Patch by Kai Nacke. This matches the gnu as output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:27:05 +00:00
Michael Liao
c16f8c5e56 Remove tailing whitespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 18:54:02 +00:00
Chad Rosier
5df2e16ba1 [inline asm] Add a test case for r180226. The specific issue is that the inline
assembly is requesting a 64-bit register, which is invalid for i386.
rdar://13731657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 17:10:21 +00:00
Rafael Espindola
e5330f77cf Use a pointer as the relocation iterator.
Since the relocation iterator walks only the relocations in one section, we
can just use a pointer and avoid fetching information about the section at
every reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 12:45:46 +00:00
Rafael Espindola
956ca7265c Clarify getRelocationAddress x getRelocationOffset a bit.
getRelocationAddress is for dynamic libraries and executables,
getRelocationOffset for relocatable objects.

Mark the getRelocationAddress of COFF and MachO as not implemented yet. Add a
test of ELF's. llvm-readobj -r now prints the same values as readelf -r.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180259 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 12:28:45 +00:00
Silviu Baranga
02066838b5 Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 09:32:33 +00:00
Rafael Espindola
06fd5bf4ea Revert "Adding object caching support to MCJIT"
This reverts commit 07f0392313.

Looks like it broke the valgrind bot:

http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 03:47:41 +00:00
Rafael Espindola
7467e5ed1c Revert "Exposing MCJIT through C API"
This reverts commit 8c31b29814.

It looks like this commit broke some bots:

http://lab.llvm.org:8011/builders/llvm-ppc64-linux2/builds/5209

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 03:19:12 +00:00
Rafael Espindola
3d3cc32f5f Don't compute a std::vector<uint8_t> just to write it out a stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 03:07:42 +00:00
Akira Hatanaka
24b56e94f6 Test case for r180241.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 02:22:07 +00:00
Akira Hatanaka
4cc3d1b910 Test case for r180238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 02:21:09 +00:00
Akira Hatanaka
089741479b [mips] Add definitions of micromips load and store instructions.
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 01:21:25 +00:00
Filipe Cabecinhas
aa27161a01 Allow users to choose identity used to sign tools.
Summary:
No change if the identity isn't defined by the makefile.

Reviewers: echristo

Differential Revision: http://llvm-reviews.chandlerc.com/D632

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 01:17:54 +00:00
Akira Hatanaka
385de77303 [mips] Add definitions of micromips shift instructions.
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 01:11:15 +00:00
Andrew Kaylor
2f5640d637 Fixing OCAML bindings for MCJIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180232 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 00:03:58 +00:00
Tom Stellard
aa6deab608 R600: Initialize BooleanVectorContents
Fixes test/CodeGen/R600/setcc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:56:18 +00:00
Tom Stellard
87cba4a4c1 R600: Use SHT_PROGBITS for the .AMDGPU.config section
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:56:14 +00:00
Andrew Kaylor
8c31b29814 Exposing MCJIT through C API
Patch by Filip Pizlo



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:33:53 +00:00
Andrew Trick
a264a20277 Fix for r180193 - MI Sched: eliminate local vreg.
Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce the test case in PR15838 (1k lines of metadata) but gave up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:19:56 +00:00
Chad Rosier
2871ba90a3 [inline asm] Fix a crasher for an invalid value type/register class.
rdar://13731657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 22:53:10 +00:00
Andrew Kaylor
034f4be273 Making invalidateInstructionCache automatic in SectionMemoryManager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 22:39:12 +00:00
Michael Gottesman
3f4613310d [objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that were once autoreleaseRV instructions.
Due to the semantics of ARC, we must be extremely conservative with autorelease
calls inserted by the frontend since ARC gaurantees that said object will be in
the autorelease pool after that point, an optimization invariant that the
optimizer must respect.

On the other hand, we are allowed significantly more flexibility with
autoreleaseRV instructions.

Often times though this flexibility is disrupted by early transformations which
transform objc_autoreleaseRV => objc_autorelease if said instruction is no
longer being used as part of an RV pair (generally due to inlining). Since we
can not tell the difference in between an autorelease put into place by the
frontend and one created through said ``strength reduction'' we can not perform
these optimizations.

The addition of this set gets around said issues by allowing us to differentiate
in between said two cases.

rdar://problem/13697741.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 22:18:18 +00:00
Michael Gottesman
0eb5e45e4b Fixed comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 22:18:15 +00:00