Chris Lattner
0ca2c8e02c
Now that compare instructions aren't lumped in with the other twoargfp instructions,
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we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14144 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-11 04:49:02 +00:00
Chris Lattner
ab8deccb82
Introduce a new FP instruction type to separate the compare cases from the
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twoarg cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14143 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-11 04:41:24 +00:00
Chris Lattner
665e661384
Add support for the setp instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14140 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-11 04:30:06 +00:00
Chris Lattner
440bbc257e
Add immediate forms of in/out. Use let to shorten lines
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12895 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-13 17:19:31 +00:00
Chris Lattner
133dbb1285
Fix issues that the local allocator has dealing with instructions that implicitly use ST(0)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12855 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-12 03:02:48 +00:00
Chris Lattner
284b496aae
No really, fix printing for LLC. I gotta get a way for CVS to whine at me if
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I have unsaved emacs buffers, geeze...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12854 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-12 01:52:04 +00:00
Chris Lattner
2fc83a5ba6
Correct printing for LLC and the encoding for the JIT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12853 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-12 01:50:04 +00:00
Chris Lattner
a1b5e160ed
Add two new instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12850 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-12 01:38:55 +00:00
Chris Lattner
490e86fed5
Add some new instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12838 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-11 20:24:15 +00:00
John Criswell
ca6ea0f137
Changes recommended by Chris:
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InstSelectSimple.cpp:
Change the checks for proper I/O port address size into an exit() instead
of an assertion. Assertions aren't used in Release builds, and handling
this error should be graceful (not that this counts as graceful, but it's
more graceful).
Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
Added the OpSize attribute to the 16 bit IN and OUT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12786 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-08 22:39:13 +00:00
John Criswell
4ffff9e2fa
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
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I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12782 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-08 20:31:47 +00:00
Chris Lattner
43ab3a8f45
Fix incorrect encoding of some ADC and SBB instuctions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12710 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:20:32 +00:00
Chris Lattner
ee98389808
The sbb instructions really ARE sbb's, not adc's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12682 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 02:02:11 +00:00
Alkis Evlogimenos
1a66731da8
Fix type in comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12611 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
8b28b6d187
Add more ADC and SBB variants
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12607 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-02 07:11:10 +00:00
Chris Lattner
1c54a85447
Add FP conditional move instructions, which annoyingly have special properties
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that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-31 22:02:13 +00:00
Chris Lattner
a5cdab7101
Fix some serious bugs in the cmov descriptions, which didn't cause a problem because
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we never generated them
Make indentation a bit more consistent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12549 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-30 20:18:02 +00:00
Alkis Evlogimenos
63dd4ff809
Add LAHF instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12424 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
a3f66842b2
Add support for a wider range of CMOV instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12336 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-12 17:59:56 +00:00
Alkis Evlogimenos
cc2a2a530f
Differentiate between extended precision floats (80-bit) and double precision floats (64-bit)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12254 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
13d362f310
Add memory operand version of conditional move.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12190 91177308-0d34-0410-b5e6-96231b3b80d8
2004-03-07 03:19:11 +00:00
Alkis Evlogimenos
7f6124cfc2
Use correct template for SHLD and SHRD instructions so that the memory
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operand size is correctly specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11997 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
8295f202d9
A big X86 instruction rename. The instructions are renamed to make
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their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 08:50:03 +00:00
Alkis Evlogimenos
8777d241cf
Use correct template for ADC instruction with memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11974 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-29 02:18:17 +00:00
Alkis Evlogimenos
da474adb21
SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
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to denote this fact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11972 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
8e475b8cfd
Floating point loads/stores act on memory operands. Rename them to
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denote this fact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11971 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
91c4b52e7f
Rename instruction templates to be easier to the human eye to
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parse. The name is now I (operand size)*. For example:
Im32 -> instruction with 32-bit memory operands.
Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11970 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
5ab29b504d
Each instruction now has both an ImmType and a MemType. This describes
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the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 22:02:05 +00:00
Alkis Evlogimenos
745502a04b
Do not generate instructions with mismatched memory/immediate sized
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operands. The X86 backend doesn't handle them properly right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11944 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84cda0f470
Further comment updates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11933 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
a643a1a528
Update comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11932 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
2eae379388
My previous commit broke the jit. The shift instructions always take
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an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.
A bug still exists:
def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11931 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28 02:56:26 +00:00
Alkis Evlogimenos
fa5229691f
Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11923 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
f9186e38d5
Fix encoding of ADD and SUB family of instructions. Also rearrange
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them so that they are consistent with AND, XOR, etc...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11922 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
169584ed45
Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11921 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
08388a4787
Add memory operand folding support for the SETcc family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11907 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
e56508eb7e
Add memory operand folding support for SHLD and SHRD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11905 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
58ec60589b
Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11903 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
e35ba65b02
Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
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consistent with the rest and also pepare for the addition of their
memory operand variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11902 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-27 06:57:05 +00:00
Chris Lattner
2d0a82570a
Add a new cmove instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11722 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-23 01:16:05 +00:00
Alkis Evlogimenos
e9118f3694
Fix argument size for MOVSX and MOVZX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11576 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-18 16:20:40 +00:00
Alkis Evlogimenos
9b9b7fc28d
These store to memory too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11558 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 17:53:48 +00:00
Chris Lattner
acce13e4cc
These store to memory, not read from it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11556 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 17:46:50 +00:00
Alkis Evlogimenos
14ffe75c9c
Add TEST and XCHG memory operand support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11550 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 15:48:42 +00:00
Alkis Evlogimenos
68bff8e15d
Add OR and XOR memory operand support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11549 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 15:33:14 +00:00
Alkis Evlogimenos
a7be982e72
Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT,
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MOVSX, and MOVZX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11546 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 09:14:23 +00:00
Alkis Evlogimenos
509d6d65b5
Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11544 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 08:49:00 +00:00
Alkis Evlogimenos
503770cfc3
Add SUB{rm,mr,mi}{8,16,32} instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11543 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 08:17:40 +00:00
Alkis Evlogimenos
69da6dba79
Add support for ADC{rm.mr}32 and SBB{rm,mr}32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11540 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 08:06:31 +00:00
Chris Lattner
e87331d11d
Fix the mneumonics for the mov instructions to have the source and destination
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order in the correct sense!! Arg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11530 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 06:28:19 +00:00
Chris Lattner
7ddc3fbd22
Fix the last crimes against nature that used the 'ir' ordering to use the
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'ri' ordering instead... no it's not possible to store a register into an
immediate!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11529 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 06:24:02 +00:00
Chris Lattner
6e173a0d9c
Rename MOVi[mr] instructions to MOV[rm]i
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11527 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 06:16:44 +00:00
Chris Lattner
4ff7876c64
Add mem forms of AND instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11521 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 05:25:50 +00:00
Chris Lattner
55b5481255
Rename the IMULri* instructions to IMULrri, as they are actually three address
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instructions. Add forms of these instructions that read from memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-17 04:26:43 +00:00
Alkis Evlogimenos
7271e0e107
Add two more variants of add. Update comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11510 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-16 23:48:42 +00:00
Chris Lattner
e0f636a068
Add some ADD instructions that take memory operands for Alkis
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11502 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-16 18:19:31 +00:00
Chris Lattner
3193556387
Add support for the 'pop' instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11451 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-14 21:06:02 +00:00
Chris Lattner
9f87a6ce6f
Urg, right. These need an input value...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11443 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-14 04:47:23 +00:00
Chris Lattner
b89abef577
add 'rep stos[bwd]' instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11441 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-14 04:45:37 +00:00
Chris Lattner
915e5e56d7
Add support for the rep movs[bwd] instructions, and emit them when code
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generating the llvm.memcpy intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11351 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-12 17:53:22 +00:00
Alkis Evlogimenos
f0339396c1
IMULri* instructions do not require their first two registers operands
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to be the same (IOW they are not two address instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11117 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-04 17:21:04 +00:00
Chris Lattner
3b904eb351
Add the ftst instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11095 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-03 07:27:50 +00:00
Chris Lattner
1580193020
No need to declare implicit uses/defs of ST0
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11081 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-02 19:57:45 +00:00
Chris Lattner
9f8fd6d9ea
Generate the fchs instruction to negate a floating point number
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11078 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-02 19:31:38 +00:00
Alkis Evlogimenos
e0bb3e766d
Remove floating point killer pass. This is now implemented in the
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instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10562 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-20 16:22:59 +00:00
John Criswell
856ba76200
Added LLVM copyright header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-21 15:17:13 +00:00
Chris Lattner
43a5ff8d40
Emit x86 instructions for: A = B op C, where A and B are 16-bit registers,
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C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.
This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version. Because these instructions are very common, this
can save a LOT of code space. For example, I sampled two benchmarks, 176.gcc
and 254.gap.
BM Old New Reduction
176.gcc 2673621 2548962 4.89%
254.gap 498261 475104 4.87%
Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc. Not bad.
Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9284 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 05:53:31 +00:00
Chris Lattner
c01d1232fe
* Rename X86::IMULr16 -> X86::IMULrr16
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* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
extra copy into a register, reducing register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9278 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 03:42:58 +00:00
Chris Lattner
f634a103ee
Add some new instructions. Wheee
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9266 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-19 19:25:35 +00:00
Chris Lattner
51970b2734
Add support for unconditional branches and for emitting JE instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7872 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-15 04:50:49 +00:00
Chris Lattner
00b40943ab
Add basic support for 16 and 32 bit function arguments!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7755 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 21:30:00 +00:00
Chris Lattner
e7e33c0543
Add (ret int) expander so that we can at least write testcases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 15:48:00 +00:00
Chris Lattner
b84fe1c636
Add patterns for multiply, and, or, and xor
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7725 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 15:23:25 +00:00
Chris Lattner
d87b59c866
add a pattern for RET, immediates no longer need to be explicitly typed
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7635 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-06 15:31:35 +00:00
Chris Lattner
02beda1221
This is the real fix for the previous register allocator problem.
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Physical registers should not float around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7587 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-05 00:48:47 +00:00
Chris Lattner
0bfd186db0
Add patterns for (mov R, R) (mov R, I) and subtracts. The moves are to enable
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testing, the subtracts are because I was in the neighborhood.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7581 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 21:18:19 +00:00
Chris Lattner
c34921dc6a
Change comments into something that TableGen can read!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7580 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 21:08:29 +00:00
Chris Lattner
c8f4587efd
transition to using let instead of set
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7564 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 04:59:56 +00:00
Chris Lattner
1cca5e3a29
Add new TableGen instruction definitions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7537 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:21 +00:00