Commit Graph

26850 Commits

Author SHA1 Message Date
NAKAMURA Takumi
b05bddb4ba Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."
It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown".

FYI, it didn't appear to add either "-O0" or "-fast-isel".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 10:55:15 +00:00
Ana Pazos
6345249972 Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 08:16:15 +00:00
Ana Pazos
1c93766aa5 Implemented Neon scalar by element intrinsics.
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:37:04 +00:00
Bill Wendling
072ebe59e2 The basic problem is that some mainstream programs cannot deal with the way
clang optimizes tail calls, as in this example:

int foo(void);
int bar(void) {
 return foo();
}

where the call is transformed to:

  calll .L0$pb
.L0$pb:
  popl  %eax
.Ltmp0:
  addl  $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
  movl  foo@GOT(%eax), %eax
  popl  %ebp
  jmpl  *%eax                   # TAILCALL

However, the GOT references must all be resolved at dlopen() time, and so this
approach cannot be used with lazy dynamic linking (e.g. using RTLD_LAZY), which
usually populates the PLT with stubs that perform the actual resolving.

This patch changes X86TargetLowering::LowerCall() to skip tail call
optimization, if the called function is a global or external symbol.

Patch by Dimitry Andric!

PR15086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195318 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:04:30 +00:00
Paul Robinson
6079f00035 Teach ISel not to optimize 'optnone' functions.
Based on work by Andrea Di Biagio.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 06:33:32 +00:00
Reed Kotler
ce10f18555 Add, to constant islands, long jumps similar to ARM far branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 05:13:23 +00:00
Hal Finkel
1e81642366 PPC popcnt[dw] do not have record forms
The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195272 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 20:54:55 +00:00
Daniel Sanders
128d90ab4a [mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo
There's no test case for this commit. This is because it is doubtful that the
incorrect behaviour can actually trigger. When MSA is not enabled, the type
legalizer should have eliminated all occurrences of patterns the affected
pseudo-instruction could possibly match before instruction selection occurs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195252 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 14:32:28 +00:00
Daniel Sanders
070fd55793 [mips][msa] Remove unused instruction class MSA_I8_X_DESC_BASE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 13:01:10 +00:00
NAKAMURA Takumi
56b09220a3 X86ISelLowering.cpp: Mark a variable VT as LLVM_ATTRIBUTE_UNUSED. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 10:55:22 +00:00
NAKAMURA Takumi
6bee54e30a Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 10:55:15 +00:00
Elena Demikhovsky
29086acc6e Fixed compilation error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 09:23:22 +00:00
Elena Demikhovsky
5cd32afac4 AVX-512: Concat 4 128-bit vectors in one 512-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 09:10:40 +00:00
Hal Finkel
eda8f6708d PPC: Optimize rldicl generation for masked shifts
Masking operations (where only some number of the low bits are being kept) are
selected to rldicl(x, 0, mb). If x is a logical right shift (which would become
rldicl(y, 64-n, n)), we might be able to fold the two instructions together:

  rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb) for n <= mb

The right shift is really a left rotate followed by a mask, and if the explicit
mask is a more-restrictive sub-mask of the mask implied by the shift, only one
rldicl is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 01:10:15 +00:00
Jack Carter
95047a8b80 long line correction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 00:12:44 +00:00
Jack Carter
0233715d74 reverts 195057 per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 20:53:28 +00:00
Cameron McInally
c5a925c198 Fix assembly operands for the SSE2 cvtsd2ss instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 14:36:00 +00:00
Simon Atanasyan
c5e99819f4 [Mips] Adjust float ABI settings in case of MIPS16 mode.
Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).

The patch reviewed by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 12:20:17 +00:00
Andrew Trick
d73d4f4ef2 Use symbolic operands in the patchpoint folding routine and fix a spilling bug.
Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 03:29:59 +00:00
Andrew Trick
8ddf988ef4 Add an abstraction to handle patchpoint operands.
Hard-coded operand indices were scattered throughout lowering stages
and layers. It was super bug prone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 03:29:56 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:17:05 +00:00
Eric Christopher
e40e68add7 Remove unused special member functions and reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:01:07 +00:00
Eric Christopher
15602d786b Fix previous commit and fully remove variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:52:38 +00:00
Eric Christopher
2a4888b347 Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195075 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:50:29 +00:00
Jiangning Liu
f11b55c5cc Implement AArch64 SISD intrinsics for vget_high and vget_low.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:46:48 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:38:31 +00:00
Jack Carter
e53969b475 [Mips] Support for MicroMips STO refactoring.
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:25:18 +00:00
Juergen Ributzka
354362524a [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 00:57:56 +00:00
Jack Carter
4c1625b3cb [Mips] MipsTargetStreamer refactoring.
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:55:27 +00:00
Reid Kleckner
a7b7a7d629 Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:08:12 +00:00
Matt Arsenault
3560dd2dcd R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:55 +00:00
Matt Arsenault
9bc4b2c0da R600/SI: Fix multiple SGPR reads when using VCC.
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:50 +00:00
Matt Arsenault
e64a289609 R600/SI: Implement add i64, but do not yet enable.
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:47 +00:00
Matt Arsenault
15703e0a71 R600/SI: Specify SSrc operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:43 +00:00
Matt Arsenault
f38be91a82 R600/SI: addc / adde i32 are legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:40 +00:00
Matt Arsenault
b2254e603d R600/SI: Match addc to S_ADD_U32.
The carry always goes to SCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:37 +00:00
Matt Arsenault
62f35fb926 R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:34 +00:00
Matt Arsenault
f53b7841a1 R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:32 +00:00
Matt Arsenault
3e38856f04 R600/SI: Move patterns to match add / sub to scalar instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:29 +00:00
Matt Arsenault
836c5133c6 R600/SI: Fix extra defs of VCC / SCC.
When replacing scalar operations with vector,
the wrong implicit output register was used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:21 +00:00
Tom Stellard
b570599c8f R600: Enable the IR structurizer by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:44 +00:00
Tom Stellard
44248e0f63 R600: Fix a crash in the AMDILCFGStrucurizer
The ifPatternMatch() function was not correctly reporting the number
of matches in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:38 +00:00
Tom Stellard
ef37e453c4 R600: Add a SubtargetFeatture for disabling the ifcvt pass.
This is useful when writing test cases for the AMDIL structurizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:33 +00:00
Tom Stellard
b4c3516b0f R600: Use lower-case for EnableIRStructurizer feature
llc converts all values passed to -mattr= to lowercase, so this
enables us to toggle this feature when using llc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:29 +00:00
Tom Stellard
204c953cd5 R600/SI: Fix illegal VGPR->SGPR copy inside of loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:20 +00:00
Tom Stellard
bf9ddd5e8f R600/SI: Fix another case of illegal VGPR->SGPR copy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:15 +00:00
Daniel Sanders
23427207ea [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)
Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:12:43 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00