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b109ea8245
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24640 Commits

Author SHA1 Message Date
Akira Hatanaka
b109ea8245 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 20:13:37 +00:00
Akira Hatanaka
d597263b94 [mips] In performDSPShiftCombine, check that all elements in the vector are 
shifted by the same amount and the shift amount is smaller than the element
size.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 19:58:23 +00:00
Chad Rosier
6804971dcf [ms-inline asm] Remove the identifier parsing logic from the AsmParser. This is 
now taken care of by the frontend, which allows us to parse arbitrary C/C++
variables.
Part of rdar://13663589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180037 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 19:42:15 +00:00
Chad Rosier
44021515d7 [ms-inline asm] Refactor/clean up the SemaLookup interface. No functional 
change indended.
Part of rdar://13663589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180028 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 17:01:46 +00:00
Eric Christopher
2c55362848 No really, don't store anything to this since it's unconditionally 
set below.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180015 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 14:11:25 +00:00
Eric Christopher
b929b13c77 Remove variable store that is never read. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180014 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 13:51:44 +00:00
Stepan Dyatkovskiy
78e3c90419 Fix for 5.5 Parameter Passing --> Stage C: 
-- C.4 and C.5 statements, when NSAA is not equal to SP.
 -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
    variadic procedure.

Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
   CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
   No exceptions, no CPRCs here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180011 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-22 13:06:52 +00:00
Jim Grosbach
0cb1019e9c Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179989 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 23:47:41 +00:00
Jakob Stoklund Olesen
ddb14ce76c Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179987 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen
2c6b5a8d33 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179985 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 21:18:03 +00:00
Tim Northover
4cc1407b84 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179977 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-21 11:57:07 +00:00
Jakob Stoklund Olesen
da8768b2dd Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179961 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 22:49:16 +00:00
Tim Northover
335dd0d1a6 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179956 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 19:31:00 +00:00
Tim Northover
75f013822b AArch64: remove useless comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179952 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 15:57:41 +00:00
Tim Northover
8b71994fde Remove unused ShouldFoldAtomicFences flag. 
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:43 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:17 +00:00
Hal Finkel
abe64dc6f7 Move PPC getSwappedPredicate for reuse 
The getSwappedPredicate function can be used in other places (such as in
improvements to the PPCCTRLoops pass). Instead of trapping it as a static
function in PPCInstrInfo, move it into PPCPredicates with other
predicate-related things.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179926 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 05:16:26 +00:00
Stephen Lin
456ca048af Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 05:14:40 +00:00
Stephen Lin
69394f2997 Test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179913 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 00:47:48 +00:00
Akira Hatanaka
97a62bf2a4 [mips] Instruction selection patterns for DSP-ASE vector shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 23:21:32 +00:00
Eli Bendersky
75299e3a95 Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm 
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:29:18 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:22:57 +00:00
Hal Finkel
87c1e42be7 Fix PPC optimizeCompareInstr swapped-sub argument handling 
When matching a compare with a subtract where the arguments of the compare are
swapped w.r.t. the arguments of the subtract, we need to negate the predicates
(or CR bit indices) of the users. This, however, is not the same as inverting
the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM
backend seems to do this correctly, but when I adapted the code for the PPC
backend, I introduced an error in this logic.

Comparison optimization is now enabled again by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179899 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:08:38 +00:00
Anton Korobeynikov
8caffc1e75 Do not mangle in MS-way the globals with magic \001 in the name. 
Based on the patch by David Nadlinger!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179889 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 21:20:56 +00:00
Chad Rosier
4acef770cf [ms-inline asm] Make code layout more canonical with iniline asm handled last. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179875 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 19:29:50 +00:00
Akira Hatanaka
f530aff9de [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 19:03:11 +00:00
Akira Hatanaka
8d99ec5748 [mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change 
operand type to uimm16.

Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 18:47:40 +00:00
Chad Rosier
e43624e345 [ms-inline asm] Refactor the parsing of identifiers. No functional change 
indended.
Part of rdar://13663589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179871 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 18:39:50 +00:00
Chad Rosier
d386843661 [ms-inline asm] Remove these asserts. C++ variables that use namespace 
qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179867 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 17:37:05 +00:00
Chad Rosier
3031ac0131 [ms-inline asm] Move this variable into the scope in which it is used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179866 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 17:32:29 +00:00
Chad Rosier
fea1f8ee7a [ms-inline asm] Make this a hard error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179865 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 17:31:39 +00:00
Chad Rosier
89ab4e4cd0 [ms-inline asm] Cleanup the dot operator implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179856 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 15:57:00 +00:00
Tim Northover
d3af696c08 ARM: Permit "sp" in ARM variant of STREXD instructions 
Patch from Mihail Popa

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 15:44:32 +00:00
Tim Northover
4521019c6f ARM: permit "sp" in ARM variants of MOVW/MOVT instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 09:58:09 +00:00
Michael Liao
0ee17006b1 Use 'array_lengthof' as possible to avoid magic numbers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 04:03:37 +00:00
Tom Stellard
48b809e6e5 R600: Add pattern for the BFI_INT instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:11:06 +00:00
Tom Stellard
ae2a8929d8 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 02:11:00 +00:00
Bill Wendling
89ec1c5c9c Use an enum instead of magic constants to improve readability. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179820 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 00:05:59 +00:00
Chad Rosier
3f1f9c3798 [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and 
AT&T dialect.  Test case for r179804 as well.
rdar://13674398 and PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 23:16:12 +00:00
Bill Wendling
2828608e8e Set the compact unwind encoding to 'requires EH DWARF' if we cannot generate a CU encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179808 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 22:55:29 +00:00
Hal Finkel
4029c3feed Disable PPC comparison optimization by default 
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do
I'm disabling this for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 22:54:25 +00:00
Chad Rosier
88eb89b89f [asm parser] Add support for predicating MnemonicAlias based on the assembler 
variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 22:35:36 +00:00
Hal Finkel
860c08cad5 Implement optimizeCompareInstr for PPC 
Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.

This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 22:15:08 +00:00
Benjamin Kramer
fcba22decb X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't available. 
This pattern started popping up in vectorized min/max reductions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 21:37:45 +00:00
Derek Schuff
2061dcf0e4 Allow misaligned stores in x86 fast-isel. 
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and
handled by the DAG-based ISel.  However, X86FastISel::X86SelectLoad() makes
no such requirement.  There doesn't appear to be an x86 architectural
correctness issue with allowing potentially unaligned store instructions.
This patch removes this restriction.

Patch by Jim Stichnot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179774 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 17:41:08 +00:00
Chad Rosier
c3a9574eed [ms-inline asm] Simplify some logic and add a FIXME for unhandled unary minus. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179765 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 16:28:19 +00:00
Chad Rosier
6c8afad198 Make this private method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179764 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 16:13:18 +00:00
Hao Liu
d050e96133 Fix for PR14824, An ARM Load/Store Optimization bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 09:11:08 +00:00
Akira Hatanaka
2fbe90cf93 [mips] Rename function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179741 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 01:00:46 +00:00
Akira Hatanaka
26aef5b7d6 [mips] DSP-ASE move from HI/LO register instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-18 00:52:44 +00:00