Commit Graph

20 Commits

Author SHA1 Message Date
Misha Brukman
7b71776401 Fix comment header, specify type of file `tablegen'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15612 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-10 17:37:14 +00:00
Brian Gaeke
3ca4fccac5 Fix file header comments and include guards -- many files have been moved or
renamed since they were last spiffed up, or they just never had proper comments
in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13148 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-25 07:04:49 +00:00
Brian Gaeke
e3d6807ab5 Great renaming: Sparc --> SparcV9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25 18:44:15 +00:00
John Criswell
856ba76200 Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-21 15:17:13 +00:00
Misha Brukman
640b9280d5 Since we now have TableGen editing modes for VIM and (X)Emacs, we no longer need
to mark TableGen description files with "C++ mode".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7841 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-14 15:16:28 +00:00
Chris Lattner
7cc7d987a4 Transition to using 'let X = y' instead of 'set X = y'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7565 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 05:03:18 +00:00
Misha Brukman
2c4fe5813c No need for a second immediate field if the class already inherits one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7182 91177308-0d34-0410-b5e6-96231b3b80d8
2003-07-15 21:27:14 +00:00
Misha Brukman
35f19cc7b2 Removed unnecessary assignment (it was taken care by a superclass) and clarified
some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7119 91177308-0d34-0410-b5e6-96231b3b80d8
2003-07-07 22:18:06 +00:00
Misha Brukman
ce14ec3901 * Force all "don't care" bits to 0 so that there are absolutely no unset bits in
the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
  actually assigned into the right portion of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7074 91177308-0d34-0410-b5e6-96231b3b80d8
2003-07-02 19:37:48 +00:00
Misha Brukman
432fba5572 Added missing directive to store the instruction name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6639 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 23:35:11 +00:00
Misha Brukman
2e7e8fadf8 Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6618 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-05 00:39:45 +00:00
Misha Brukman
9dc3ede509 Added instruction format class 3.15 and floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6594 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-04 02:26:14 +00:00
Misha Brukman
2ee9fa11a2 Store instructions are different from other Format 3.1/3.2 instructions in that
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6564 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03 03:20:14 +00:00
Misha Brukman
13292a3347 * Removed unused classes: the rd field is always mentioned as the last reg.
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6560 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03 01:11:58 +00:00
Misha Brukman
e085a9d279 Added MOVR (move int reg on register condition), aka comparison with zero.
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02 21:16:54 +00:00
Misha Brukman
33cc12319c The 'rd' register is consistently mentioned last in instruction definitions.
Created new classes from which instructions inherit their ordering of fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 06:25:19 +00:00
Misha Brukman
c89d256e95 The actual order of parameters in a 2-reg-immediate assembly instructions is
"rs1, imm, rd": most importantly, rd goes last.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6456 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31 04:22:26 +00:00
Misha Brukman
9b03633265 Because the format of the shift instructions is `shift r, shcnt, r', the
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 18:06:10 +00:00
Brian Gaeke
9604416192 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 08:02:14 +00:00
Misha Brukman
dafa504341 * Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 03:31:43 +00:00