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117 Commits

Author SHA1 Message Date
Alp Toker
ae43cab6ba Fix known typos 
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 17:20:08 +00:00
Tom Stellard
35f321dde5 R600: Disable the BFE pattern 
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason.  I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199918 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 18:49:33 +00:00
Tom Stellard
39210ac1c6 R600: Add some missing CF instruction definitions to the .td files. 
reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199841 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 21:55:44 +00:00
Tom Stellard
f2194d3ab3 R600: CF_PUSH is the same on Evergreen and Cayman 
reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199839 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 21:55:41 +00:00
Tom Stellard
b1d24c51fc R600: MOVA is vector only 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199827 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 19:24:24 +00:00
Tom Stellard
37ee312f77 R600: Allow ftrunc 
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-20 05:11:55 +00:00
Vincent Lejeune
7043c7a35e R600: Workaround for cayman loop bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196121 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 17:29:37 +00:00
Tom Stellard
496dbfe7b9 R600: Add support for ISD::FROUND 
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 21:23:20 +00:00
Tom Stellard
0f39827340 R600/SI: Fixing handling of condition codes 
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-22 23:07:58 +00:00
Tom Stellard
a2b4eb6d15 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 23:36:50 +00:00
Vincent Lejeune
70a7d5ddb4 R600: Use function inputs to represent data stored in gpr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 22:10:24 +00:00
Vincent Lejeune
6639f066e1 R600: Clear the VPM bit of export instructions. 
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192552 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:55:57 +00:00
Vincent Lejeune
a2f1317f09 R600: Add a ldptr intrinsic to support MSAA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 16:00:33 +00:00
Vincent Lejeune
dfef7cbfc6 R600: add a pass that merges clauses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:58 +00:00
Vincent Lejeune
5b00e833fa R600: Enable -verify-machineinstrs in some tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:38 +00:00
Tom Stellard
9c598cfebc R600: Fix handling of NAN in comparison instructions 
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-28 02:50:50 +00:00
Tom Stellard
12d43f9baf SelectionDAG: Try to expand all condition codes using getCCSwappedOperands() 
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-28 02:50:38 +00:00
Aaron Watry
546dcc5ddc R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 20:17:42 +00:00
Tom Stellard
79916948e1 R600: Add support for local memory atomic add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-05 18:38:09 +00:00
Vincent Lejeune
b3df27d440 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:30 +00:00
Tom Stellard
a01cdea9c6 R600: Add support for i8 and i16 local memory loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:59 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:49 +00:00
Tom Stellard
ec484277dd R600: Add support for i16 and i8 global stores 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:12:06 +00:00
Tom Stellard
4781d314b7 R600: Add support for v4i32 stores on Cayman 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188518 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:12:00 +00:00
Tom Stellard
e7ac2ed1c2 R600: Add IsExport bit to TableGen instruction definitions 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:11:51 +00:00
Tom Stellard
e560d526a1 R600: Change the RAT instruction assembly names so they match the docs 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188515 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:11:46 +00:00
Tom Stellard
67ca7b1bb0 R600/SI: Handle MSAA texture targets 
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-14 22:22:14 +00:00
Tom Stellard
692ee102eb R600: Add 64-bit float load/store support 
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 15:23:42 +00:00
Tom Stellard
af2ea2a4fb Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions" 
This reverts commit 3f1de26cb5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 20:43:03 +00:00
Vincent Lejeune
3f1de26cb5 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:35 +00:00
Vincent Lejeune
acf7350385 R600: Remove predicated_break inst 
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).

There is no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187510 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 19:31:14 +00:00
Tom Stellard
8ea83d4999 R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary 
These are really the same address space in hardware.  The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access.  When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187006 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 23:54:56 +00:00
Tom Stellard
10205d5a73 R600: Add support for 24-bit MAD instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186923 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:49 +00:00
Tom Stellard
3f5d63b956 R600: Add support for 24-bit MUL instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:42 +00:00
Tom Stellard
eb643b9b37 R600: Improve support for < 32-bit loads 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186921 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:35 +00:00
Tom Stellard
a7eea0568c R600: Use KCache for kernel arguments 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:48:18 +00:00
Tom Stellard
2bb20fd2bf R600: Clean up extended load patterns 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186914 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 01:47:52 +00:00
Vincent Lejeune
272458bd06 R600: Don't emit empty then clause and use alu_pop_after 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186725 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-19 21:45:15 +00:00
Vincent Lejeune
f2cfef8172 R600: Do not predicated basic block with multiple alu clause 
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:33 +00:00
Vincent Lejeune
c6f13db656 R600: Use DAG lowering pass to handle fcos/fsin 
NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185940 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:11 +00:00
Vincent Lejeune
f79b9b8593 R600: Print Export Swizzle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-09 15:03:03 +00:00
Vincent Lejeune
8f9fbd67c3 R600: Support schedule and packetization of trans-only inst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-29 19:32:43 +00:00
Tom Stellard
e3d4cbc7d2 R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:47:08 +00:00
Tom Stellard
cedcfee405 R600: Add support for GROUP_BARRIER instruction 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:46:59 +00:00
Tom Stellard
7e9381951e R600: Add ALUInst bit to tablegen definitions v2 
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-28 15:46:53 +00:00
Tom Stellard
5e48a0e9ae R600: Use new getNamedOperandIdx function generated by TableGen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 21:22:18 +00:00
Tom Stellard
d67d029b6d R600: Add support for i32 loads from the constant address space on Cayman 
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184821 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-25 02:39:30 +00:00
Aaron Watry
6c4b8fe9dd R600: Fix spelling error in comment 
our -> or

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184756 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-24 16:57:57 +00:00
Vincent Lejeune
98f5cf8000 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:26 +00:00
Tom Stellard
d6055262d2 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:30 +00:00