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b6ab51e829
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191 Commits

Author SHA1 Message Date
Bob Wilson
b6ab51e829 Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78460 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 06:13:25 +00:00
Bob Wilson
64efd90f8c Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78459 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 05:53:00 +00:00
Evan Cheng
861986401e It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-07 00:34:42 +00:00
Bob Wilson
b36ec86c01 Implement Neon VST[234] operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 18:47:44 +00:00
Bob Wilson
0cedab9a0d Neon does not actually have VLD{234}.64 instructions. 
These operations will have to be synthesized from other instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-06 00:24:27 +00:00
Bob Wilson
4a3d35abef Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. 
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-05 00:49:09 +00:00
Bob Wilson
a6d658620f Lower CONCAT_VECTOR during legalization instead of matching it during isel. 
Add a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-03 20:36:38 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 01:43:45 +00:00
David Goodwin
07337c0fcf Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 22:45:52 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:56:48 +00:00
Evan Cheng
d83360694a Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 23:59:01 +00:00
Owen Anderson
eed707b1e6 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 23:12:02 +00:00
David Goodwin
5ff58b5c3a Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:16:18 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Evan Cheng
78dd9dbdfb Eliminate a redudant check Eli pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76762 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 18:08:05 +00:00
Evan Cheng
af9e7a7c20 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-21 00:31:12 +00:00
David Goodwin
31e7eba06f Use t2LDRri12 for frame index loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-20 15:55:39 +00:00
David Goodwin
7ecc850cf1 Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75789 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:50:19 +00:00
Owen Anderson
9adc0abad3 Move EVER MORE stuff over to LLVMContext. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 23:09:55 +00:00
David Goodwin
4cb73525a9 Check for PRE_INC and POST_INC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75683 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 21:29:29 +00:00
David Goodwin
419c615087 hasThumb2() does not mean we are compiling for thumb, must also check isThumb(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75660 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-14 18:48:51 +00:00
Evan Cheng
2f297df02e Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 07:08:13 +00:00
Evan Cheng
446c428bf3 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-11 06:43:01 +00:00
Evan Cheng
5c874172ac Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit. 
Note, we are not yet generating these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 22:21:59 +00:00
David Goodwin
f1daf7d8ab Use common code for both ARM and Thumb-2 instruction and register info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 23:10:31 +00:00
Evan Cheng
e7cbe4118b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 21:03:57 +00:00
Torok Edwin
dac237e182 Implement changes from Chris's feedback. 
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-08 20:53:28 +00:00
Evan Cheng
e253c951b3 Add Thumb2 movcc instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 20:39:03 +00:00
Evan Cheng
5b9fcd1c8e Add some more Thumb2 multiplication instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-07 01:17:28 +00:00
Evan Cheng
4fbb9960ad Sign extending pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 23:16:11 +00:00
Evan Cheng
e88d5cee9d Thumb2 pre/post indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 07:28:31 +00:00
Evan Cheng
af4550f826 Factor out ARM indexed load matching code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74681 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-02 01:23:32 +00:00
Bob Wilson
8b024a5eb5 Add a new addressing mode for NEON load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-01 23:16:05 +00:00
David Goodwin
6647cea111 Thumb-2 load and store double description. But nothing yet creates them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 22:50:01 +00:00
David Goodwin
5e47a9a6e4 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-30 18:04:13 +00:00
Evan Cheng
055b0310f8 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 07:51:04 +00:00
Evan Cheng
9cb9e6778c Renaming for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-27 02:26:13 +00:00
Anton Korobeynikov
d49ea77cbc Split thumb-related stuff into separate classes. 
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 21:28:53 +00:00
Evan Cheng
e870af4837 Code clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 19:38:34 +00:00
Evan Cheng
e499f97058 Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-23 18:14:38 +00:00
Bob Wilson
5bafff36c7 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 23:27:02 +00:00
Bob Wilson
e64e3cf9ad Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops 
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73887 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-22 17:29:13 +00:00
Anton Korobeynikov
52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-17 18:13:58 +00:00
Anton Korobeynikov
dada95b5b3 Revert hunk commited by accident 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73097 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:57:18 +00:00
Anton Korobeynikov
0eebf653a7 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-08 22:53:56 +00:00
Bob Wilson
224c244f56 Fix pr4091: Add support for "m" constraint in ARM inline assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-19 05:53:42 +00:00
Jim Grosbach
30eae3c022 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-07 20:34:09 +00:00
Evan Cheng
9d7b5309c2 tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-26 19:09:01 +00:00
Chris Lattner
8c4d1b2bcf fix PR3538 for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64384 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-12 17:38:23 +00:00
Dale Johannesen
f5f5dce897 Eliminate remaining non-DebugLoc version of getTargetNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-02-06 19:16:40 +00:00