Eric Christopher
b74558ad3e
Floating point stores have a 3rd addressing mode type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7
factor out a simple helper function to create a label for PC-relative
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instructions (PICADD, PICLDR, et.al.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935
PC-relative pseudo instructions are lowered and printed directly. Any encounter
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with one in the generic printing code is an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041
Add MC-inst handling for tPICADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
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value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
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and shift instructions on ARM. Update the tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107
Rework arm fast isel branch and compare code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e
Hook up verbose asm comment printing for SOImm operands in MC printer
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:25:10 +00:00
Dan Gohman
d8c0a51362
Avoid emitting a PIC base register if no PIC addresses are needed.
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This fixes rdar://8396318.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
568eeedea7
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:46:17 +00:00
Jim Grosbach
c686e33d12
handle the upper16/lower16 target operand flags on symbol references for MC
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instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:25:25 +00:00
Chris Lattner
40cc3f8783
fix rdar://8444631 - encoder crash on 'enter'
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What a weird instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
Jim Grosbach
a28abbe245
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 16:25:52 +00:00
NAKAMURA Takumi
cdd7fb7853
AlphaSchedule.td: 7bit-ize.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 09:56:43 +00:00
Chris Lattner
35aa94b229
fix rdar://8438816 - unrecognized 'fildq' instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 20:46:38 +00:00
Jim Grosbach
b74ca9d631
MC-ization of the PICLDR pseudo. Next up, adding the other variants
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(PICLDRB, et. al.) and PICSTR*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:43:25 +00:00
Jim Grosbach
1d51c41a45
Make sure to promote single precision floats to double before extracting them
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from the APFloat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:37:30 +00:00
Kalle Raiskila
1cd1b0b283
Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
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This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Bob Wilson
de0ae8f83d
Remove support for "dregpair" operand modifier, now that it is no longer being
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used for anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:55:00 +00:00
Bob Wilson
823611bfba
When expanding ARM pseudo registers, copy the existing predicate operands
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instead of using default predicates on the expanded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 04:25:37 +00:00
Jim Grosbach
a8e47b3319
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
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unnecessary dtor for MCOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 03:45:21 +00:00
Bob Wilson
ea606bb76b
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:32 +00:00
Bob Wilson
9d4ebc0eb8
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
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register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 00:31:02 +00:00
Jim Grosbach
765c4d9477
Add support for the 'lane' modifier on vdup operands
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 22:13:23 +00:00
Jakob Stoklund Olesen
06f264e504
Remember VLDMQ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:11 +00:00
Jakob Stoklund Olesen
31bbc51ac9
Add missing break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:40:09 +00:00
Jim Grosbach
60396975be
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
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moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:04:54 +00:00
Jim Grosbach
a4c3c8f28d
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
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functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 20:26:25 +00:00
Jim Grosbach
f1c3eb37ae
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
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merge the common cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:52:17 +00:00
Jim Grosbach
7e2c04fd05
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
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if the register is a member of the SPR register class directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:44:57 +00:00
Jim Grosbach
d8be410d4b
Reduce dependencies in the ARM MC instruction printer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:27:50 +00:00
Jim Grosbach
8b7fa198c3
Fix spelling typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:50 +00:00
Jim Grosbach
754578b565
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
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between the compiler back end and the MC libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 19:26:06 +00:00
Jim Grosbach
26edbcb8d5
Add support for floating point immediates to MC instruction printing. ARM
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VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 18:47:08 +00:00
Jakob Stoklund Olesen
d64816a8d0
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
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Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:27:09 +00:00
Bob Wilson
3a951829fe
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
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encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d
the darwin9-powerpc buildbot keeps consistently crashing,
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backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:53:07 +00:00
Jakob Stoklund Olesen
34327856d9
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
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forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:36:26 +00:00
Bob Wilson
064312de86
Spelling fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:28:21 +00:00
Chris Lattner
d0bcc9a015
lcall and ljmp always default to lcalll and ljmpl. This finally
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wraps up r8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:30:20 +00:00
Chris Lattner
cbb442640f
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
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for call. Add this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:25:21 +00:00
Chris Lattner
250b948f21
Disambiguate lcall/ljmp to the 32-bit version. This happens
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even in 64-bit mode apparently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:14:54 +00:00
Chris Lattner
6c1b3b1e32
fix the encoding of sldt GR16 to have the 0x66 prefix, and
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add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:45:10 +00:00
Chris Lattner
cfad564043
implement aliases for shld/shrd, part of rdar://8418316
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:37:18 +00:00
Chris Lattner
e9e16a36d9
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:33:27 +00:00
Chris Lattner
84f362d891
add various broken forms of fnstsw. I didn't add the %rax
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version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:15:16 +00:00
Chris Lattner
8f777a205e
add some aliases for f[u]comi, part of rdar://8431422
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:08:38 +00:00
Chris Lattner
2d592d10a5
add a bunch of aliases for fp operations with no operand,
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rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:04:33 +00:00