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b7ba5781e6
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2308 Commits

Author SHA1 Message Date
Johnny Chen
b7ba5781e6 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 01:29:25 +00:00
Johnny Chen
c5f413a74c Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 00:57:50 +00:00
Jim Grosbach
fceabef52c try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 00:03:13 +00:00
Johnny Chen
a271174771 Renamed NVdImmFrm to N1RegModImmFrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 23:09:14 +00:00
Johnny Chen
841e828702 Fix typo in the comment for N3VX class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:35:03 +00:00
Johnny Chen
be7849ee73 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:30:12 +00:00
Johnny Chen
3ae9a57c74 Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 21:25:38 +00:00
Johnny Chen
927b88f771 Add New NEON Format NVdVmImmFrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 20:40:44 +00:00
Bob Wilson
df9a4f0591 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 18:54:46 +00:00
Bob Wilson
011355944b Fix bad indentation, 80-column violations, and trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 17:23:59 +00:00
Johnny Chen
785516adc5 Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 16:43:47 +00:00
Bob Wilson
c289a0252b Rename some instructions to match the corresponding NEON opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:26:18 +00:00
Bob Wilson
11d9899759 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 06:20:33 +00:00
Bob Wilson
621f195243 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-23 05:25:43 +00:00
Bob Wilson
62ef3c8910 Rename one more NEON instruction that I missed earlier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 20:31:39 +00:00
Bob Wilson
052ba45bf8 Regroup some instructions. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:22:06 +00:00
Bob Wilson
a6979754da Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:13:18 +00:00
Bob Wilson
58393bc3fd Remove some redundant instruction classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 18:02:38 +00:00
Bob Wilson
39842553e8 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:43:10 +00:00
Jeffrey Yasskin
fa72340ba0 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-22 16:13:21 +00:00
Daniel Dunbar
5d067fe158 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:36:22 +00:00
Bob Wilson
c88d072293 pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:20:40 +00:00
Bob Wilson
226036ee73 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:13:40 +00:00
Bob Wilson
d5fadaf56e Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:57:36 +00:00
Bob Wilson
4f4f93f9d6 Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:45:18 +00:00
Bob Wilson
068b18be0d Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 21:15:48 +00:00
Bob Wilson
25eb5013d0 Add VST1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:54:36 +00:00
Bob Wilson
a1023645f8 Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:47:18 +00:00
Bob Wilson
41315282f9 Tidy some more comments and whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:39:53 +00:00
Bob Wilson
92cb9321a1 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 20:10:51 +00:00
Bob Wilson
667a13e1be Tidy some comments and whitespace for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 19:57:03 +00:00
Bob Wilson
95ffecd4fe Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:35:24 +00:00
Bob Wilson
00bf1d93d7 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 18:14:26 +00:00
Bob Wilson
99493b2b53 Add VLD1 instructions with address register writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 17:59:03 +00:00
Bob Wilson
55c9cb5a22 Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:34:02 +00:00
Bob Wilson
98330ff8e3 Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 06:05:13 +00:00
Johnny Chen
caa608e97c Add NLdStFrm Format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 00:17:00 +00:00
Johnny Chen
e86425f224 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 23:50:27 +00:00
Bob Wilson
76a312b7d1 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 22:51:32 +00:00
Johnny Chen
81f04d59f6 Renumber LdStExFrm from 28 to 11 and shift the existing format values to make 
room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 17:39:00 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Jeffrey Yasskin
c3e45f1ee2 Remove a memory leak from ThumbTargetMachine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:25:28 +00:00
Daniel Dunbar
6b7c2cf5d4 Fix -Asserts warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 03:18:23 +00:00
Bob Wilson
50622ce8cf Update comment to refer to the right filename. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 23:57:57 +00:00
Anton Korobeynikov
341ab138fb Get rid of target-specific fp <-> int nodes when still I'm here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov
f0d500768d Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 22:35:37 +00:00
Anton Korobeynikov
6755d97a62 Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 22:35:02 +00:00
Chris Lattner
b7d5226a4e fix some buggy ops concatentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 21:06:54 +00:00
Bob Wilson
95808328b4 Refactor NEON ld/st instructions to hardcode class arguments that are constants. 
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 20:18:39 +00:00
Johnny Chen
6c8648b4c9 Revert 98745 with respect to the addition of NEONFrm subformats for disassembly. 
There is a better way coming up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98777 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-17 23:26:50 +00:00