6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-14 20:57:01 +00:00
Code Issues Projects Releases Wiki Activity
85,413 Commits 39 Branches 0 Tags 277 MiB
bc96bcdaf9
Commit Graph

1333 Commits

Author SHA1 Message Date
Reed Kotler
c94a38ff17 1. Add load/store words from the stack 
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 02:26:24 +00:00
Akira Hatanaka
cb39aa05af MIPS DSP: ABSQ_S.PH instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:09:21 +00:00
Akira Hatanaka
23bb38f034 MIPS DSP: SHLL.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:05:08 +00:00
Akira Hatanaka
833f7a5c4b MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 04:08:42 +00:00
Akira Hatanaka
451b0e7b8a MIPS DSP: CMPU.EQ.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:58:34 +00:00
Akira Hatanaka
a216401621 MIPS DSP: ADDU.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:13:59 +00:00
Akira Hatanaka
01f7089bca MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:15:57 +00:00
Akira Hatanaka
2df483efb3 MIPS DSP: all the remaining instructions which read or write accumulators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:11:20 +00:00
Akira Hatanaka
fd89e6ffda MIPS DSP: add support for extract-word instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:05:42 +00:00
Akira Hatanaka
5e69cef21b MIPS DSP: add functions which decode DSP and accumulator registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:01:10 +00:00
Akira Hatanaka
cc46fe591a MIPS DSP: add code necessary for pseudo instruction lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:59:07 +00:00
Akira Hatanaka
7e105bcc3a MIPS DSP: add bitcast patterns between vectors and int. 
No test cases. These patterns will get tested along with dsp intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:56:38 +00:00
Akira Hatanaka
7509ec18d1 MIPS DSP: add vector load/store patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:50:59 +00:00
Akira Hatanaka
b500e9249a Add case clauses for returning dsp accumulator encoding values in function 
getMipsRegisterNumbering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164720 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:27:24 +00:00
Akira Hatanaka
81571d3e0f Add DSP accumulator registers and register class. Remove hi/lo registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:25:21 +00:00
Akira Hatanaka
c878f3899c Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:18:19 +00:00
Akira Hatanaka
3757ff1a68 Initialize boolean variables in MipsSubtarget's constructor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 23:07:11 +00:00
Reed Kotler
289b5d7f02 blank line for test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164640 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 22:34:20 +00:00
Chad Rosier
2590c2e1e9 Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 22:57:55 +00:00
Chad Rosier
00796a1b15 Rather then have a wrapper function, have tblgen instantiate the implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 19:32:29 +00:00
Akira Hatanaka
ef5fc952e8 MIPS DSP: Add immediate leaves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 00:07:12 +00:00
Akira Hatanaka
67032b27cd MIPS DSP: Add predicates and instruction template. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 00:06:06 +00:00
Akira Hatanaka
b430cecc0e Add MIPS DSP register classes. Set actions of DSP vector operations and override 
TargetLowering's callback functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164431 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 23:58:31 +00:00
Akira Hatanaka
6fad5e742d SelectionDAG node enums for MIPS DSP nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164430 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 23:52:47 +00:00
Akira Hatanaka
1024f290d1 Add MIPS accumulator and DSP control registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 23:48:37 +00:00
Akira Hatanaka
a9adbf6df7 Add flags and feature bits for mips dsp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164428 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 23:41:49 +00:00
Chad Rosier
d717a066c6 [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 22:21:26 +00:00
NAKAMURA Takumi
b377635592 Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164354 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 02:21:30 +00:00
Akira Hatanaka
0fdf3b029b Properly save and restore RA and Mips16 callee save registers S0,S1 
Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164349 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-21 01:08:16 +00:00
Akira Hatanaka
37236515cf Revert r164051. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 18:08:25 +00:00
Roman Divacky
536a88ad5b When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.

Fixes PR11212.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-18 16:08:49 +00:00
Akira Hatanaka
ff1547890a Make sure there is enough room for RA. getStackSize needs to be cleaned up but 
we will do that when we implement the full save/restore.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164051 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-17 20:02:42 +00:00
Craig Topper
dd100d831b Remove unused private fields to silence -Wunused-private-field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163973 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 17:08:51 +00:00
Akira Hatanaka
5a7dd43f04 Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and 
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 01:52:08 +00:00
Akira Hatanaka
f934d159ae Handled unaligned load/stores properly in Mips16 
Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163956 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-15 01:02:03 +00:00
Dmitri Gribenko
c5252da873 Fix Doxygen issues: 
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
  with the rest of the codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-14 14:57:36 +00:00
Akira Hatanaka
99258f6755 mips16 fixes. 
1. Add MoveR3216
2. Correct spelling for Move32R16

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-14 03:21:56 +00:00
Akira Hatanaka
e6ac7d69d3 mips16: When copying operands in a conditional branch instruction, allow for 
immediate operands to be copied.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163811 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-13 17:12:37 +00:00
Akira Hatanaka
afc945b614 Misc. 
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163753 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 23:27:55 +00:00
Michael Liao
6c7ccaa3fd Fix PR11985 
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 21:43:09 +00:00
Dmitri Gribenko
67c8978617 Fix a couple of Doxygen comment issues pointed out by -Wdocumentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 16:59:47 +00:00
Dmitri Gribenko
2de0572cae Remove redundant semicolons which are null statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:26:47 +00:00
Benjamin Kramer
1ac4587eb3 Make helper function static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163504 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 11:52:14 +00:00
Benjamin Kramer
38539ebc2b MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163383 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-07 09:47:42 +00:00
Jack Carter
04376ebe9f The Mips standalone assembler aliased instruction support. 
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.

These changes are in the instruction td file.

Test cases included

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-07 01:42:38 +00:00
Jack Carter
acbea45573 The Mips standalone assembler intial directive support. 
Actually these are just stubs for parsing the directives.
Semantic support will come later.

Test cases included

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-07 00:48:02 +00:00
Jack Carter
f740d6e328 The Mips standalone assembler fpu instruction support. 
Test cases included

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-07 00:23:42 +00:00
David Blaikie
35e3aed169 Remove unused variable introduced by r163346. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163359 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 23:31:29 +00:00
Jack Carter
6b96c3f71f The Mips standalone assembler memory instruction support. 
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw

Test case included

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 20:00:02 +00:00
Jack Carter
a7570a3d86 There are some Mips instructions that are lowered by the 
assembler such as shifts greater than 32. In the case 
of direct object, the code gen needs to do this lowering 
since the assembler is not involved.

With the advent of the llvm-mc assembler, it also needs 
to do the same lowering.

This patch makes that specific lowering code accessible 
to both the direct object output and the assembler.

This patch does not affect generated output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 02:31:34 +00:00