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93 Commits

Author SHA1 Message Date
Evan Cheng
21d03f2de0 lib/Target/Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28386 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 20:42:07 +00:00
Chris Lattner
966454129d Move function-live-in-handling code from the sdisel code to the scheduler. 
This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28315 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-16 06:10:58 +00:00
Evan Cheng
8820ad5154 Fixing 2006-05-01-SchedCausingSpills.ll; some clean up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-13 08:22:24 +00:00
Owen Anderson
07000c6f01 Refactor a bunch of includes so that TargetMachine.h doesn't have to include 
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-12 06:33:49 +00:00
Evan Cheng
626da3d9ae Duh. That could take a long time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28235 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-12 06:05:18 +00:00
Evan Cheng
13d41b9d72 Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28230 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-12 01:58:24 +00:00
Evan Cheng
e165a78551 Refactor scheduler code. Move register-reduction list scheduler to a 
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28226 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-11 23:55:42 +00:00
Chris Lattner
8b915b4ed2 Remove and simplify some more machineinstr/machineoperand stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 18:16:01 +00:00
Chris Lattner
2d90ac7ca6 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 18:05:43 +00:00
Chris Lattner
ea50fabfd4 Remove a bunch more SparcV9 specific stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-04 01:15:02 +00:00
Owen Anderson
a69571c799 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-03 01:29:57 +00:00
Nate Begeman
37efe67645 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 18:53:45 +00:00
Chris Lattner
45053fc7fc fix spello 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27053 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 07:15:07 +00:00
Chris Lattner
54a30b9639 TargetData doesn't know the alignment of vectors :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26884 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-20 01:51:46 +00:00
Chris Lattner
2f5806c2b3 Move some simple-sched-specific instance vars to the simple scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26690 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 07:42:02 +00:00
Chris Lattner
1e433c59e0 prune #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26689 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 07:37:35 +00:00
Chris Lattner
e76074ab89 move some simple scheduler methods into the simple scheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26688 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 07:35:21 +00:00
Chris Lattner
8c7ef0599c Make EmitNode take a SDNode instead of a NodeInfo* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26687 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 07:28:36 +00:00
Chris Lattner
df3750642a Move the VRBase field from NodeInfo to being a separate, explicit, map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26686 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 07:25:12 +00:00
Chris Lattner
be24e5996c Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26682 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-10 06:34:51 +00:00
Chris Lattner
b0d21ef20c Change the interface for getting a target HazardRecognizer to be more clean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-08 04:25:59 +00:00
Chris Lattner
a93dfcd40a When a hazard recognizer needs noops to be inserted, do so. This represents 
noops as null pointers in the instruction sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26564 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-05 23:51:47 +00:00
Evan Cheng
404cb4f9fa Added an offset field to ConstantPoolSDNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-25 09:54:52 +00:00
Chris Lattner
daf6bc6347 Pass all the flags to the asm printer, not just the # operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26362 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:50:58 +00:00
Chris Lattner
fd6d282a71 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26361 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 19:18:20 +00:00
Chris Lattner
ed18b6896e Refactor operand adding out to a new AddOperand method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26358 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-24 18:54:03 +00:00
Chris Lattner
c3a9f8d31c Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-23 19:21:04 +00:00
Chris Lattner
948d9668a7 Make MachineConstantPool entries alignments explicit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26071 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-09 02:23:13 +00:00
Jeff Cohen
f3afef3b3a Fix VC++ warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25975 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 16:20:31 +00:00
Evan Cheng
cccf1232a6 Get rid of some memory leaks identified by Valgrind 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25960 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 06:49:00 +00:00
Chris Lattner
dc19b70d24 Add initial support for immediates. This allows us to compile this: 
int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:26:14 +00:00
Evan Cheng
b8973bd8f5 Allow the specification of explicit alignments for constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25855 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 22:23:14 +00:00
Chris Lattner
6656dd1a78 Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 02:03:41 +00:00
Chris Lattner
acc43bf4ab Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an 
ISD::INLINEASM node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25668 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 23:28:04 +00:00
Evan Cheng
46c01cfe9f No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25608 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 18:54:24 +00:00
Evan Cheng
e0a5832374 Keep track of bottom / top element of a set of flagged nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25600 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 09:13:41 +00:00
Evan Cheng
4ef1086749 Factor out more instruction scheduler code to the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25532 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 07:01:07 +00:00
Evan Cheng
a9c2091cd3 Do some code refactoring on Jim's scheduler in preparation of the new list 
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25493 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-21 02:32:06 +00:00
Duraid Madina
f65d917f71 purity++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25041 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-29 05:59:19 +00:00
Jim Laskey
e81aecbae6 Disengage DEBUG_LOC from non-PPC targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 20:51:37 +00:00
Jim Laskey
d845582d4a Amend comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24861 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 16:32:26 +00:00
Jim Laskey
de48ee28a3 Create a strong dependency for loads following stores. This will leave a 
latency period between the two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24860 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 16:30:13 +00:00
Jeff Cohen
18840db533 Keep VC++ happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24835 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 22:20:05 +00:00
Jim Laskey
bd2b621486 Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24816 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 04:40:52 +00:00
Jim Laskey
9022ed955a Groups were not emitted if the dominator node and the node in the ordering list 
were not the same node.  Ultimately the test was bogus.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24815 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 03:59:21 +00:00
Chris Lattner
a5282d8df2 Simplify code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24806 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 01:03:46 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:51:06 +00:00
Evan Cheng
61ca74bc3a Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24523 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-30 02:04:11 +00:00
Chris Lattner
de202b3cda Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding 
nodes to the graph.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24263 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-09 23:47:37 +00:00
Chris Lattner
4012eb2137 Explicitly initialize some instance vars 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24247 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-08 21:54:57 +00:00