Rafael Espindola
ec46ea34dc
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29727 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-16 14:43:33 +00:00
Rafael Espindola
a1ab92d8b7
correctly set LocalAreaOffset of TargetFrameInfo
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29589 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-09 17:37:45 +00:00
Rafael Espindola
7a53bd0890
fix the spill code
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-09 16:41:12 +00:00
Rafael Espindola
2c8cdc6c1a
fix the loading of the link register in emitepilogue
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29580 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-09 13:15:47 +00:00
Rafael Espindola
46adf8119d
change the addressing mode of the str instruction to reg+imm
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-08 20:35:03 +00:00
Rafael Espindola
1a00946817
initial support for variable number of arguments
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29567 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-08 13:02:29 +00:00
Rafael Espindola
44819cb20a
implemented sub
...
correctly update the stack pointer in the prologue and epilogue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29244 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-21 12:26:16 +00:00
Rafael Espindola
355746359e
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-18 17:00:30 +00:00
Rafael Espindola
a4e64359aa
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 11:36:48 +00:00
Rafael Espindola
aefe14299a
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-10 01:41:35 +00:00
Rafael Espindola
49e4415587
handle the "mov reg1, reg2" case in isMoveInstr
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28945 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-27 21:52:45 +00:00
Rafael Espindola
58421d7d08
initial implementation of ARMRegisterInfo::eliminateFrameIndex
...
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-18 00:08:07 +00:00
Rafael Espindola
dc124a234a
implement movri
...
add a stub LowerFORMAL_ARGUMENTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 21:45:49 +00:00
Evan Cheng
0f3ac8d8d4
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:12:58 +00:00
Rafael Espindola
7bc59bc395
added a skeleton of the ARM backend
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
