Commit Graph

51 Commits

Author SHA1 Message Date
Daniel Sanders
6cc2e1a132 [mips] Add assembler support for .set msa/nomsa directive.
Summary:
These directives are used to toggle whether the assembler accepts MSA-specific instructions or not.

Patch by Matheus Almeida and Toma Tabacu.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4783


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215099 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 12:03:36 +00:00
Daniel Sanders
52a51e197f Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 15:05:51 +00:00
Daniel Sanders
b70b4892a4 Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
This commit causes multiple lld tests to fail. Reverting while I investigate the issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212945 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:43:45 +00:00
Daniel Sanders
05aee6b5f4 [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.

Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.

Differential Revision: http://reviews.llvm.org/D4487


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212939 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:02:14 +00:00
Daniel Sanders
e99ebb9b2f [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no '.module oddspreg' is used
Differential Revision: http://reviews.llvm.org/D4486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 10:26:15 +00:00
Simon Atanasyan
b2b56ed1a6 [Mips] Support SHT_MIPS_ABIFLAGS section type flag in the llvm-readobj,
obj2yaml and yaml2obj tools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 15:28:54 +00:00
Daniel Sanders
fbdb8e1eac [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums
Summary:
Follow on to r212519 to improve the encapsulation and limit the scope of the enums.

Also merged two very similar parser functions, fixed a bug where ASE's
were not being reported, and marked CPR1's as being 128-bit when MSA is
enabled.

Differential Revision: http://reviews.llvm.org/D4384


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 10:11:38 +00:00
Daniel Sanders
b3fa233048 [mips] Work around inconsistency in llvm-mc's placement of fixup markers
Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 13:35:24 +00:00
Matheus Almeida
db5b7e016a [mips] Move disassembler test (test_2r_msa64) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208594 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:59:34 +00:00
Matheus Almeida
4d28469a8d [mips] Move disassembler test (Mips MSA test_vec) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208592 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:31:45 +00:00
Matheus Almeida
d8527e2578 [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208590 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:26:53 +00:00
Matheus Almeida
e9cd60685b [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208589 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:23:45 +00:00
Matheus Almeida
e18828fb2b [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:20:46 +00:00
Matheus Almeida
f666827156 [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:16:59 +00:00
Matheus Almeida
86992065e6 [mips] Move disassembler test (Mips MSA test_bit) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:10:00 +00:00
Matheus Almeida
5e3662ae95 [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
correct folder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 16:03:20 +00:00
Matheus Almeida
3f14ca5e30 [mips][msa] Add DLSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 12:05:17 +00:00
Matheus Almeida
9c45241485 [mips][msa] Add insert.d instruction.
This instruction is only available on Mips64 cores that implement the MSA ASE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 13:31:20 +00:00
Matheus Almeida
72d4223ff5 [mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 15:12:02 +00:00
Matheus Almeida
ba67c2a4ee [mips][msa] Add copy_{u,s}.d.
These instructions are only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 14:05:28 +00:00
Matheus Almeida
0f040daba7 [mips][msa] Update format of RUN lines for every MSA MC test.
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-18 17:31:21 +00:00
Matheus Almeida
d0ee4c5302 [mips][msa] Remove unneeded triple directive in MSA MC tests.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-18 11:06:13 +00:00
Matheus Almeida
4faa2b38fb [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 11:06:22 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 10:43:11 +00:00
Matheus Almeida
f7b6bac262 [mips][msa] Direct Object Emission support for the LSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 13:20:07 +00:00
Matheus Almeida
5cb5ff8b14 [mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-22 09:43:32 +00:00
Matheus Almeida
348da8d6b5 [mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 13:07:13 +00:00
Matheus Almeida
b14ad46549 [mips][msa] Direct Object Emission support for LDI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:56:20 +00:00
Matheus Almeida
f6d4cff9b1 [mips][msa] Direct Object Emission support for MOVE.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:43:54 +00:00
Matheus Almeida
006cff8d7b [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:26:50 +00:00
Matheus Almeida
cebd401022 [mips][msa] Direct Object Emission of SPLAT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:07:26 +00:00
Matheus Almeida
f89f66e61b [mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 11:47:56 +00:00
Matheus Almeida
9672a89c71 [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 13:07:39 +00:00
Matheus Almeida
e89c50acc8 [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:57:18 +00:00
Matheus Almeida
01436ba306 [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:38:17 +00:00
Matheus Almeida
29adbe8464 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 12:22:43 +00:00
Matheus Almeida
45ecbfc8e5 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 11:49:30 +00:00
Matheus Almeida
21d60f02c3 This reverts 192447 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:58:32 +00:00
Matheus Almeida
abba71663e This reverts r192449 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:56:12 +00:00
Matheus Almeida
62a69eee5a [mips][msa] Direct Object Emission for the majority of the ELM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:39:49 +00:00
Matheus Almeida
6f36ea5c47 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-11 13:29:36 +00:00
Jack Carter
bdf8015cff [mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 18:05:18 +00:00
Jack Carter
b0247157c6 [mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:58:07 +00:00
Jack Carter
70f556140f [mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:52:33 +00:00
Jack Carter
2641f5e412 [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register

Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:43:04 +00:00
Jack Carter
1327c08922 [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 21:31:43 +00:00
Jack Carter
9fa81ab838 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 00:09:46 +00:00
Jack Carter
4167b88cf5 [mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:56:25 +00:00