Commit Graph

105584 Commits

Author SHA1 Message Date
Alexander Kornienko
c58b079d23 Add FileCheck -implicit-check-not option to allow stricter tests without adding too many CHECK-NOTs manually.
Summary:
Add FileCheck -implicit-check-not option which allows specifying a
pattern that should only occur in the input when explicitly matched by a
positive check. This feature allows checking tool diagnostics in a way
clang -verify does it for compiler diagnostics.

The option has been tested on a number of clang-tidy checks, I'll post a link to
the clang-tidy patch to this thread.

Once there's an agreement on the general direction, I can add tests and
documentation.

Reviewers: djasper, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4462

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212810 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 12:39:32 +00:00
Quentin Colombet
52c50f5ec5 [X86] Fix the inversion of low and high bits for the lowering of MUL_LOHI.
Also add a few comments.

<rdar://problem/17581756>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212808 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 12:08:23 +00:00
Marcello Maggioni
ca4b18075c Added test for commit r212802 that was missing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 10:36:00 +00:00
Marcello Maggioni
a533de6f59 Fixup PHIs in LowerSwitch when a Leaf node is not emitted.
This commit fixes bug http://llvm.org/bugs/show_bug.cgi?id=20103.

Thanks to Qwertyuiop for the report and the proposed fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212802 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 10:34:36 +00:00
Adam Nemet
11c9a50611 [X86] AVX512: Improve readability of isCDisp8
No functional change.  As I was trying to understand this function, I found
that variables were reused with confusing names and the broadcast case was a
bit too implicit.  Hopefully, this is an improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212795 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 05:23:25 +00:00
Adam Nemet
fcc56eb31f [X86] AVX512: Simplify logic in isCDisp8
It was computing the VL/n case as:
  MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize

ElemByteSize not only falls out but VectorByteSize/Divider now actually
matches the definition of VL/n.

Also some formatting fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212794 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 05:23:12 +00:00
David Blaikie
181826c623 Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""
This reverts commit r212776.

Nope, still seems to be failing on the sanitizer bots... but hey, not
the msan self-host anymore, it's failing in asan now. I'll start looking
there next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 02:42:57 +00:00
Mark Heffernan
9853f94520 Partially fix PR20058: reduce compile time for loop unrolling with very high count by reducing calls to SE->forgetLoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212782 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 23:30:06 +00:00
Lang Hames
eb2fff64dd [RuntimeDyld] Replace a crufty old ARM RuntimeDyld test with a new one that uses
RuntimeDyldChecker.

This allows us to remove one of the six remaining object files in the LLVM
source tree.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212780 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 23:29:11 +00:00
Lang Hames
5cfcad187b [RuntimeDyld] Improve error diagnostic in RuntimeDyldChecker.
The compiler often emits assembler-local labels (beginning with 'L') for use in
relocation expressions, however these aren't included in the object files.
Teach RuntimeDyldChecker to warn the user if they try to use one of these in an
expression, since it will never work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 23:26:20 +00:00
David Blaikie
e14048c25a Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."
Committed in r212205 and reverted in r212226 due to msan self-hosting
failure, I believe I've got that fixed by r212761 to Clang.

Original commit message:

"Originally committed in r211723, reverted in r211724 due to failure
cases found and fixed (ArgumentPromotion: r211872, Inlining: r212065),
committed again in r212085 and reverted again in r212089 after fixing
some other cases, such as debug info subprogram lists not keeping track
of the function they represent (r212128) and then short-circuiting
things like LiveDebugVariables that build LexicalScopes for functions
that might not have full debug info.

And again, I believe the invariant actually holds for some reasonable
amount of code (but I'll keep an eye on the buildbots and see what
happens... ).

Original commit message:

PR20038: DebugInfo: Inlined call sites where the caller has debug info
but the call itself has no debug location.

This situation does bad things when inlined, so I've fixed Clang not to
produce inlinable call sites without locations when the caller has debug
info (in the one case where I could find that this occurred). This
updates the PR20038 test case to be what clang now produces, and readds
the assertion that had to be removed due to this bug.

I've also beefed up the debug info verifier to help diagnose these
issues in the future, and I hope to add checks to the inliner to just
assert-fail if it encounters this situation. If, in the future, we
decide we have to cope with this situation, the right thing to do is
probably to just remove all the DebugLocs from the inlined
instructions."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212776 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:59:39 +00:00
David Blaikie
9fe4d6bcd4 This test case doesn't actually need the inliner to reproduce the input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:57:40 +00:00
Jan Vesely
865527a09b R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering

v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
    add comment about using FP_TO_SINT for uints

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:40:21 +00:00
Jan Vesely
bb917c2f8a SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer
Move the code to a helper function to allow calls from TypeLegalizer.

No functionality change intended

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
Reviewed-by: Owen Anderson <resistor@mac.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:40:18 +00:00
Brad Smith
e39f7f95bc Use the integrated assembler by default on OpenBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:37:28 +00:00
Zoran Jovanovic
fc6a659676 [mips] Emit two CFI offset directives per double precision SDC1/LDC1
instead of just one for FR=1 registers
Differential Revision: http://reviews.llvm.org/D4310


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212769 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:23:30 +00:00
Andrea Di Biagio
4d3b6131c7 Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.
Add test cases where we don't expect to trigger the combine optimizations
introduced at revision 212748.

No functional change intended.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212756 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 18:59:41 +00:00
Matt Arsenault
b730c3d28d Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.""
Don't try to convert the select condition type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212750 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 18:21:04 +00:00
Andrea Di Biagio
3996e5290a [DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches the DAGCombiner how to fold shuffles according to the
following new rules:
  1. shuffle(shuffle(x, y), undef) -> x
  2. shuffle(shuffle(x, y), undef) -> y
  3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
  4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef)

The backend avoids to combine shuffles according to rules 3. and 4. if
the resulting shuffle does not have a legal mask. This is to avoid introducing
illegal shuffles that are potentially expanded into a sub-optimal sequence of
target specific dag nodes during vector legalization.

Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers
the new rules when combining shuffles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 18:04:55 +00:00
Akira Hatanaka
60079c18bc [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.
Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable
macro-fusion.

<rdar://problem/15680770>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 18:00:53 +00:00
Eric Christopher
b5a006e88f Add the CSR company and the Kalimba DSP processor to Triple.
Patch by Matthew Gardiner with fixes by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212745 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 17:26:54 +00:00
Eric Christopher
282eda9b74 Make it possible for the Subtarget to change between function
passes in the mips back end. This, unfortunately, required a
bit of churn in the various predicates to use a pointer rather
than a reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212744 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 17:26:51 +00:00
Duncan P. N. Exon Smith
5b8419d32e InstCombine: Fix a crash in Descale for multiply-by-zero
Fix a crash in `InstCombiner::Descale()` when a multiply-by-zero gets
created as an argument to a GEP partway through an iteration, causing
-instcombine to optimize the GEP before the multiply.

rdar://problem/17615671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 17:13:27 +00:00
David Majnemer
c1a6d65d21 IR: Aliases don't belong to an explicit comdat
Aliases inherit their comdat from their aliasee, they don't have an
explicit comdat.

This fixes PR20279.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 16:26:10 +00:00
Hal Finkel
b1beb01d82 Feeding isSafeToSpeculativelyExecute its DataLayout pointer (in Sink)
This is the one remaining place I see where passing
isSafeToSpeculativelyExecute a DataLayout pointer might matter (at least for
loads) -- I think I got the others in r212720. Most of the other remaining
callers of isSafeToSpeculativelyExecute only use it for call sites (or
otherwise exclude loads).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212730 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 16:07:11 +00:00
David Majnemer
9478f0a6ff Mips: Silence a -Wcovered-switch-default
Remove a default label which covered no enumerators, replace it with a
llvm_unreachable.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212729 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 16:04:04 +00:00
Zoran Jovanovic
0ef47114d3 [mips] Added FPXX modeless calling convention.
Differential Revision: http://reviews.llvm.org/D4293


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212726 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 15:36:12 +00:00
Arnaud A. de Grandmaison
a9af0558b2 [AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:

  bic  Rd, Rn, #imm  ->  and Rd, Rn, #~imm
  bics Rd, Rn, #imm  ->  ands Rd, Rn, #~imm
  orn  Rd, Rn, #imm  ->  orr Rd, Rn, #~imm
  eon  Rd, Rn, #imm  ->  eor Rd, Rn, #~imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 15:12:26 +00:00
Hal Finkel
73118c4128 Feeding isSafeToSpeculativelyExecute its DataLayout pointer
isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the
past, this was mainly used to make better decisions regarding divisions known
not to trap, and so was not all that important for users concerned with "cheap"
instructions. However, now it also helps look through bitcasts for
dereferencable loads, and will also be important if/when we add a
dereferencable pointer attribute.

This is some initial work to feed a DataLayout pointer through to callers of
isSafeToSpeculativelyExecute, generally where one was already available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212720 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 14:41:31 +00:00
Tim Northover
6b0ac2aa02 AArch64: correctly fast-isel i8 & i16 multiplies
We were asking for a register for type i8 or i16 which caused an assert.

rdar://problem/17620015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212718 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 14:18:46 +00:00
Daniel Sanders
24a071b8c5 [mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.

This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
  do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
  statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
  instructions to/from odd registers are guaranteed not to appear for any
  reason. Once this has been established, the user can then re-enable
  -modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
  O32 FP64A is used as the ABI. This is intended to provide almost all
  functionality of an FR=1 processor but can also be executed on a FR=0 core
  with the assistance of a hardware compatibility mode which emulates FR=0
  behaviour on an FR=1 processor.

* Added '.module oddspreg' and '.module nooddspreg' each of which update
  the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
  doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
  than trying to maintain them in the same format they will be emitted in.

There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.

Differential Revision: http://reviews.llvm.org/D4383


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 13:38:23 +00:00
Zinovy Nis
a2bc403710 [x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is Pavel Chupin).
This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow.

Differential Revision: http://reviews.llvm.org/D4181



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212716 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 13:03:26 +00:00
Chandler Carruth
cdbdfa28d1 [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous
to the zero-extend-vector-inreg node introduced previously for the same
purpose: manage the type legalization of widened extend operations,
especially to support the experimental widening mode for x86.

I'm adding both because sign-extend is expanded in terms of any-extend
with shifts to propagate the sign bit. This removes the last
fundamental scalarization from vec_cast2.ll (a test case that hit many
really bad edge cases for widening legalization), although the trunc
tests in that file still appear scalarized because the the shuffle
legalization is scalarizing. Funny thing, I've been working on that.

Some initial experiments with this and SSE2 scenarios is showing
moderately good behavior already for sign extension. Still some work to
do on the shuffle combining on X86 before we're generating optimal
sequences, but avoiding scalarization is a huge step forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212714 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 12:32:32 +00:00
Richard Sandiford
35dda8a53c [SystemZ] Use SystemZCallingConv.td to define callee-saved registers
Just a clean-up.  No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:44:37 +00:00
NAKAMURA Takumi
2f7fa8922f SpecialCaseList.h: Fix -Wdocumentation with \code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:39:59 +00:00
NAKAMURA Takumi
e93de7fb73 llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212709 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:37:39 +00:00
NAKAMURA Takumi
5290734b8f Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."
This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212708 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:37:28 +00:00
Richard Sandiford
446067b143 [SystemZ] Tweak instruction format classifications
There's no real need to have Shift as a separate format type from Binary.
The comments for other format types were too specific and in some cases
no longer accurate.

Just a clean-up, no behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212707 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:29:23 +00:00
Chandler Carruth
a4e7f05a28 [x86] Add another combine that is particularly useful for the new vector
shuffle lowering: match shuffle patterns equivalent to an unpcklwd or
unpckhwd instruction.

This allows us to use generic lowering code for v8i16 shuffles and match
the unpack pattern late.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212705 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:09:29 +00:00
Richard Sandiford
9aa8beb9d6 [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA
These instructions aren't used for codegen since the original L*DB instructions
are suitable for fround.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212703 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 11:00:55 +00:00
Richard Sandiford
beefa3ada0 [SystemZ] Avoid using i8 constants for immediate fields
Immediate fields that have no natural MVT type tended to use i8 if the
field was small enough.  This was a bit confusing since i8 isn't a legal
type for the target.  Fields for short immediates in a 32-bit or 64-bit
operation use i32 or i64 instead, so it would be better to do the same
for all fields.

No behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212702 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 10:52:51 +00:00
Richard Sandiford
b350ec7ec6 [SystemZ] Fix FPR dwarf numbering
The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6,
F1, F3, F5, F7, F8, etc., which matches the pairing of registers for
long doubles.  E.g. a long double stored in F0 is paired with F2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212701 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 10:45:11 +00:00
Daniel Sanders
b0b3161567 Make it possible for ints/floats to return different values from getBooleanContents()
Summary:
On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer
comparisons return 0 or 1.

Updated the various uses of getBooleanContents. Two simplifications had to be
disabled when float and int boolean contents differ:
- ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially
  discoverable (i.e. when the condition of the VSELECT is a SETCC node).
- visitVSELECT (select C, 0, 1) -> (xor C, 1).
  Come to think of it, this one could test for the common case of 'C'
  being a SETCC too.

Preserved existing behaviour for all other targets and updated the affected
MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low'
variable was counting in the wrong direction because it thought it could simply
add the result of the comparison.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D4389


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 10:18:12 +00:00
Chandler Carruth
977aab501d [x86] Expand the target DAG combining for PSHUFD nodes to be able to
combine into half-shuffles through unpack instructions that expand the
half to a whole vector without messing with the dword lanes.

This fixes some redundant instructions in splat-like lowerings for
v16i8, which are now getting to be *really* nice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212695 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 09:57:36 +00:00
Chandler Carruth
dc90a3ab8f [x86] Tweak the v16i8 single input special case lowering for shuffles
that splat i8s into i16s.

Previously, we would try much too hard to arrange a sequence of i8s in
one half of the input such that we could unpack them into i16s and
shuffle those into place. This isn't always going to be a cheaper i8
shuffle than our other strategies. The case where it is always going to
be cheaper is when we can arrange all the necessary inputs into one half
using just i16 shuffles. It happens that viewing the problem this way
also makes it much easier to produce an efficient set of shuffles to
move the inputs into one half and then unpack them.

With this, our splat code gets one step closer to being not terrible
with the new experimental lowering strategy. It also exposes two
combines missing which I will add next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 09:16:40 +00:00
Hal Finkel
8892dbf2bb A test case for not asserting in isDereferenceablePointer upon unsized types
This is the test case for r212687.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212688 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 07:04:37 +00:00
Hal Finkel
5ee0267e49 Fix isDereferenceablePointer not to try to take the size of an unsized type.
I'll add a test-case shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212687 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 06:06:11 +00:00
Hal Finkel
a739834446 Allow isDereferenceablePointer to look through some bitcasts
isDereferenceablePointer should not give up upon encountering any bitcast. If
we're casting from a pointer to a larger type to a pointer to a small type, we
can continue by examining the bitcast's operand. This missing capability
was noted in a comment in the function.

In order for this to work, isDereferenceablePointer now takes an optional
DataLayout pointer (essentially all callers already had such a pointer
available). Most code uses isDereferenceablePointer though
isSafeToSpeculativelyExecute (which already took an optional DataLayout
pointer), and to enable the LICM test case, LICM needs to actually provide its DL
pointer to isSafeToSpeculativelyExecute (which it was not doing previously).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212686 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 05:27:53 +00:00
Saleem Abdulrasool
344517923c MC: modernise for loop
Convert a for loop to range bsaed form.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212684 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 04:50:09 +00:00
Saleem Abdulrasool
09f505a0a5 MC: add and use an accessor for WinCFI
This adds a utility method to access the WinCFI information in bulk and uses
that to iterate rather than requesting the count and individually iterating
them.  This is in preparation for restructuring WinCFI handling to enable more
clear sharing across architectures to enable unwind information emission for
Windows on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212683 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 04:50:06 +00:00