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10407 Commits

Author SHA1 Message Date
Dan Gohman
6bbe671e1c Make GlobalValue alignment consistent with load, store, and alloca 
alignment, fixing silent truncation of alignment values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 20:56:48 +00:00
Dan Gohman
138aa2a82b Define a maximum supported alignment value for load, store, and 
alloca instructions (constrained by their internal encoding),
and add error checking for it. Fix an instcombine bug which
generated huge alignment values (null is infinitely aligned).
This fixes undefined behavior noticed by John Regehr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 20:12:04 +00:00
Nate Begeman
51409214d7 Implement a vectorized algorithm for <16 x i8> << <16 x i8> 
This is about 4x faster and smaller than the existing scalarization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 00:21:48 +00:00
Stuart Hastings
3c73a6b650 Testcase for r109556. Radar 8198362. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 23:15:25 +00:00
Nate Begeman
bdcb5afb77 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. 
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 22:37:06 +00:00
Devang Patel
8b5749da2a Update tests to not rely on input file's absolute path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109521 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 18:13:53 +00:00
Nate Begeman
e0efc216eb Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 18:02:18 +00:00
Tobias Grosser
56029271f9 Make coff-dump.py executable and add python as executable for this script. 
This fixes the MC/COFF/basic-coff.ll test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109497 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 09:01:26 +00:00
Michael J. Spencer
dfd30187c6 Make MC use Windows COFF on Windows and add tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-27 06:46:15 +00:00
Anton Korobeynikov
b5a0ef99f8 Currently EH lowering code expects typeinfo to be global only. 
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 18:45:39 +00:00
Owen Anderson
88dafec7f9 Fix a test with malformed IR. Not sure why this didn't fail before. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109422 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 18:44:56 +00:00
Dan Gohman
6ebfd72f37 Fix SCEVExpander::visitAddRecExpr so that it remembers the induction variable 
it inserted rather than using LoopInfo::getCanonicalInductionVariable to
rediscover it, since that doesn't work on non-canonical loops. This fixes
infinite recurrsion on such loops; PR7562.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 18:28:14 +00:00
Dan Gohman
38d49ad083 Avoid depending on LCSSA implicitly pulling in LoopSimplify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 18:00:43 +00:00
Bruno Cardoso Lopes
3c8e1bee63 Support x86 "eiz" and "riz" pseudo index registers in the assembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-24 00:06:39 +00:00
Matt Fleming
19d92fcae2 Consolidate the ELF section directive tests into a single file as 
suggested by Chris Lattner.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109290 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 23:40:41 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases, 
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 22:39:59 +00:00
Bruno Cardoso Lopes
6d7019bcc4 Move AVX encoding tests to different files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109269 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 21:25:26 +00:00
Dan Gohman
cd20c6fb18 Use the proper type for shift counts. This fixes a bootstrap error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 21:08:12 +00:00
Stuart Hastings
79ced813d7 Test case to insure template function declaration refers to correct filename. Radar 8063111. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109258 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 20:15:49 +00:00
Bruno Cardoso Lopes
f528d2b438 Add AVX version of CLMUL instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 18:41:12 +00:00
Dan Gohman
a4f4d699ec DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 
are not demanded. This often allows the anyext to be folded away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 18:03:30 +00:00
Bruno Cardoso Lopes
6b7e9168a4 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 00:54:35 +00:00
Bruno Cardoso Lopes
fb583a9842 Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 21:18:49 +00:00
Tobias Grosser
f96b006367 Add new RegionInfo pass. 
The RegionInfo pass detects single entry single exit regions in a function,
where a region is defined as any subgraph that is connected to the remaining
graph at only two spots.
Furthermore an hierarchical region tree is built.
Use it by calling "opt -regions analyze" or "opt -view-regions".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 07:46:31 +00:00
Eric Christopher
9a9d275dc7 Custom lower the memory barrier instructions and add support 
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-22 02:48:34 +00:00
Evan Cheng
4a863e2c75 More register pressure aware scheduling work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:53:58 +00:00
Bruno Cardoso Lopes
2b69143083 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 23:53:50 +00:00
Eric Christopher
ab695889c6 Baby steps towards ARM fast-isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 22:26:11 +00:00
Bruno Cardoso Lopes
e29f37f6a1 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 21:37:59 +00:00
Dan Gohman
872814ae04 Disallow null as a named metadata operand. 
Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.

One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109028 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 18:54:18 +00:00
Rafael Espindola
bc56501435 Fix calling convention on ARM if vfp2+ is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 11:38:30 +00:00
Bruno Cardoso Lopes
cf6ca03128 Add AVX only vzeroall and vzeroupper instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 08:56:24 +00:00
Eric Christopher
80a16b0569 Turn this test on again after the llvm-gcc change in r108986. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 04:54:06 +00:00
Eric Christopher
302313fc09 Update this to use a "valid" alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 04:51:24 +00:00
Bruno Cardoso Lopes
7d7d15a159 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
4b13f3cf3d Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
1154f426d7 Add new AVX vextractf128 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 23:19:02 +00:00
Matt Fleming
a7f9563c01 Include some tests for the recently committed ELF section directive 
handlers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108938 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 21:37:30 +00:00
Eric Christopher
de8d40503e Testcase for llvm-gcc commit r108910. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 20:32:47 +00:00
Bruno Cardoso Lopes
e1c29be6f0 Add new AVX instruction vinsertf128 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 19:44:51 +00:00
Dan Gohman
fc3678a346 Fix SCEV denormalization of expressions where the exit value from 
one loop is involved in the increment of an addrec for another
loop. This fixes rdar://8168938.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108863 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 17:06:20 +00:00
Jim Grosbach
f27ca42552 update tests for smarter BIC usage 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 16:16:48 +00:00
Duncan Sands
6bf8eee264 The same problem was being tracked in PR7652. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 15:52:32 +00:00
Bruno Cardoso Lopes
46773793cb Fix PR7174, a couple o Mips fixes: 
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.

Patch by stetorvs@gmail.com



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 08:37:04 +00:00
Bruno Cardoso Lopes
29e9daa750 Fix Mips PR7473. Patch by stetorvs@gmail.com 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 07:58:51 +00:00
Bruno Cardoso Lopes
7a2b701ef6 x86_32 tests for vbroadcast 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes
43945d99de Add AVX vbroadcast new instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
94143ee625 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 23:32:44 +00:00
Dan Gohman
c6e59b71f5 After a custom inserter, in a block which has constant instructions, 
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 22:48:56 +00:00
Daniel Dunbar
77e2dd7bb2 X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-19 20:44:16 +00:00