Commit Graph

28649 Commits

Author SHA1 Message Date
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 05:30:21 +00:00
Benjamin Kramer
fda5e19b96 X86: Don't transform shifts into ands when the sign bit is tested.
Should unbreak MultiSource/Benchmarks/mediabench/g721/g721encode/encode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207145 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 20:51:37 +00:00
Reid Kleckner
710c1a449d Add 'musttail' marker to call instructions
This is similar to the 'tail' marker, except that it guarantees that
tail call optimization will occur.  It also comes with convervative IR
verification rules that ensure that tail call optimization is possible.

Reviewers: nicholas

Differential Revision: http://llvm-reviews.chandlerc.com/D3240

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207143 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 20:14:34 +00:00
Andrea Di Biagio
35f9e1aa49 [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics.
This patch:
- Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and
   'int_x86_rdtscp') as GCCBuiltin intrinsics;
- Teaches the backend how to lower the two new builtins;
- Introduces a common function to lower READCYCLECOUNTER dag nodes
  and the two new rdtsc/rdtscp intrinsics;
- Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll'
  correctly verifies that both READCYCLECOUNTER and the two new intrinsics
  work fine for both 64bit and 32bit Subtargets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207127 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 17:18:27 +00:00
Matt Arsenault
2dbbd17394 R600/SI: Use address space in allowsUnalignedMemoryAccesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 17:08:26 +00:00
David Blaikie
45966fa1f1 Spread some const around for non-mutating uses of MCSymbolData.
I discovered this const-hole while attempting to coalesnce the Symbol
and SymbolMap data structures. There's some pending issues with that,
but I figured this change was easy to flush early.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207124 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 16:59:40 +00:00
Matheus Almeida
25fb047609 [mips] Remove non-ascii character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207123 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 16:31:10 +00:00
Tim Northover
a05d37e1f4 AArch64: print NEON lists with a space.
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 14:06:20 +00:00
Evgeniy Stepanov
23a4885f59 [asan] Use MCInstrInfo in inline asm instrumentation.
Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 13:29:34 +00:00
Tim Northover
d4daf1762d AArch64/ARM64: allow negative addends, at least on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207111 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:38 +00:00
Tim Northover
421c65b9b4 ARM64: support relocated "TBZ/TBNZ" instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:34 +00:00
Tim Northover
332497fc56 AArch64/ARM64: support relocated ADR instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:30 +00:00
Tim Northover
4fec4077fc AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiers
We only need assembly support, so it's fairly easy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:27 +00:00
Tim Northover
f909da2bec ARM64: shut up warning about variable only used in assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207106 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:22:12 +00:00
Tim Northover
d4b4f400e8 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands
These can have different relocations in ELF. In particular both:

    b.eq global
    ldr x0, global

are valid, giving different relocations. The only possible way to distinguish
them is via a different fixup, so the operands had to be separated throughout
the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:12:10 +00:00
Tim Northover
b62ba5eca0 AArch64/ARM64: implement BFI optimisation
ARM64 was not producing pure BFI instructions for bitfield insertion
operations, unlike AArch64. The approach had to be a little different (in
ISelDAGToDAG rather than ISelLowering), and the outcomes aren't identical but
hopefully this gives it similar power.

This should address PR19424.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:11:53 +00:00
Evgeniy Stepanov
fd46b84ddd [asan] Fix instrumentation of x86 intel syntax inline assembly.
Patch by Yuri Gorshenin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207092 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 09:56:15 +00:00
Benjamin Kramer
f43438b6c3 X86: Emit test instead of constant shift + compare if the shift result is unused.
This allows us to compile
  return (mask & 0x8 ? a : b);
into
  testb $8, %dil
  cmovnel %edx, %esi
instead of
  andl  $8, %edi
  shrl  $3, %edi
  cmovnel %edx, %esi

which we formed previously because dag combiner canonicalizes setcc of and into shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207088 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 08:15:31 +00:00
Stepan Dyatkovskiy
5c025f2f6e Fix for PR18921, "vmov" part.
Added support for bytes replication feature, so it could be GAS compatible.

E.g. instructions below:
"vmov.i32 d0, 0xffffffff"
"vmvn.i32 d0, 0xabababab"
"vmov.i32 d0, 0xabababab"
"vmov.i16 d0, 0xabab"
are incorrect, but we could deal with such cases.

For first one we should emit:
"vmov.i8 d0, 0xff"
For second one ("vmvn"):
"vmov.i8 d0, 0x54"
For last two instructions it should emit:
"vmov.i8 d0, 0xab"

P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code.
Just for keeping method bodies in harmony with themselves.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 06:03:01 +00:00
Quentin Colombet
28a24ca471 [ARM64] Fix the information we give to the peephole optimizer for comparison.
ANDS does not use the same encoding scheme as other xxxS instructions (e.g.,
ADDS). Take that into account to avoid wrong peephole optimization.

<rdar://problem/16693089>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207020 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 20:43:38 +00:00
Quentin Colombet
3ce58b3f60 [X86] Fix missing/wrong scheduling model found by code inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207014 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 19:30:26 +00:00
NAKAMURA Takumi
d5a7c3f2ec X86AsmParser.cpp: Fix memory leak at replacing movsd to movsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206991 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 14:51:35 +00:00
Evgeniy Stepanov
d6af41b2eb Create MCTargetOptions.
For now it contains a single flag, SanitizeAddress, which enables
AddressSanitizer instrumentation of inline assembly.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 11:16:03 +00:00
James Molloy
c2547d0429 [ARM64] Fix formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206967 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 10:50:32 +00:00
James Molloy
57683b8aba [ARM64] Add a big endian version of the ARM64 target machine, and update all users.
This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206965 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 10:26:40 +00:00
Alexey Volkov
4231346c8d Fixing typos in commit r206957
Differential Revision: http://reviews.llvm.org/D3451


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206960 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 10:20:31 +00:00
Alexey Volkov
2e5f39ee0f [X86] Silvermont new scheduler model
This model is not final and work is still in progress.
However there are substantial improvements on integer tests mainly because of better RAL with new scheduler.

Differential Revision: http://reviews.llvm.org/D3451


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206957 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 08:57:09 +00:00
Elena Demikhovsky
3890a42255 X86Disassembler - fixed a bug in immediate print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 07:21:04 +00:00
Kevin Qin
81ea345894 [ARM64] Enable feature predicates for NEON / FP / CRYPTO.
AArch64 has feature predicates for NEON, FP and CRYPTO instructions.
This allows the compiler to generate code without using FP, NEON
or CRYPTO instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 06:22:48 +00:00
Kevin Enderby
29c96f133e Fix the assembler to print a better relocatable expression error
diagnostic that includes location information.

Currently if one has this assembly:

	.quad (0x1234 + (4 * SOME_VALUE))

where SOME_VALUE is undefined ones gets the less than
useful error message with no location information:

% clang -c x.s
clang -cc1as: fatal error: error in backend: expected relocatable expression

With this fix one now gets a more useful error message
with location information:

% clang -c x.s 
x.s:5:8: error: expected relocatable expression
 .quad (0x1234 + (4 * SOME_VALUE))
       ^

To do this I plumbed the SMLoc through the MCObjectStreamer
EmitValue() and EmitValueImpl() interfaces so it could be used
when creating the MCFixup.

rdar://12391022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206906 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 17:27:29 +00:00
Matt Arsenault
3682fdabef R600: Emit error instead of unreachable on function call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:42:00 +00:00
Tom Stellard
baf1d45ec2 R600/SI: Reorganize SIInstructions.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206902 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 16:33:57 +00:00
Elena Demikhovsky
b84cc10c3c AVX-512: store and truncstore for i1 values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206897 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 14:13:10 +00:00
Tim Northover
8b36f98fd5 AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 12:45:42 +00:00
Lang Hames
20850bba80 [X86] Require HasBMI2 for the new BZHI tablegen patterns.
Evidently tablegen doesn't infer this from the HasBMI2 predicate on the BZHI
instructions. This should fix the recent bot failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 12:04:53 +00:00
Robert Khasanov
c13297fa76 [AVX512] Implemented integer conversions up/down with masking.
Added encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206884 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 11:36:19 +00:00
Lang Hames
404fa73ef6 [X86] Remove Tablegen def of X86bzhi SDNode: It's not needed as of r206879.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206880 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:50:46 +00:00
Lang Hames
390592d968 [X86] Use tablegen instead of DAG combines to match BZHI instructions, as
suggested by Ben Kramer in review of r206738.

Thanks again Ben!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206879 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:41:56 +00:00
Matheus Almeida
59d57db258 [mips] Clang-format MipsAsmParser.
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206878 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:15:54 +00:00
Tim Northover
0e277d18bb AArch64/ARM64: add patterns for scalar_to_vector/extract pairs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:18 +00:00
Tim Northover
74bd57b16b ARM: disable emission of __XYZvfp in soft-float environment.
The point of these calls is to allow Thumb-1 code to make use of the VFP unit
to perform its operations. This is not desirable with -msoft-float, since most
of the reasons you'd want that apply equally to the runtime library.

rdar://problem/13766161

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 10:10:09 +00:00
Lang Hames
53b4d83b63 [X86] Don't use BZHI for short masks (>=32 bits). Thanks to Ben Kramer for the
review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206869 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 07:40:34 +00:00
Matt Arsenault
073440f3d4 R600: Change how vector truncating stores are packed.
Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 04:11:14 +00:00
Matt Arsenault
3ddf868b04 R600: Make sign_extend_inreg legal.
Don't know why I didn't just do this in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:49:30 +00:00
Jiangning Liu
0240286c23 [AArch64] Enable global merge pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 03:33:26 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:41:26 +00:00
Chandler Carruth
3d5cd01d37 [cleanup] Fix two headers where we included a standard library header
after including the generated code from tablegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206841 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:28:45 +00:00
Chandler Carruth
cd30379386 [cleanup] Fix another place where we were including the tablegen'ed code
of a '.inc' file before including actual headers. In this case we had
both duplicated a header's include and were including a standard header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206840 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:25:17 +00:00
Chandler Carruth
58f58c97f0 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some
system headers above the includes of generated '.inc' files that
actually contain code. In a few targets this was already done pretty
consistently, but it wasn't done *really* consistently anywhere. It is
strictly cleaner IMO and necessary in a bunch of places where the
DEBUG_TYPE is referenced from the generated code. Consistency with the
necessary places trumps. Hopefully the build bots are OK with the
movement of intrin.h...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:03:14 +00:00
Chandler Carruth
283b399377 [Modules] Make Support/Debug.h modular. This requires it to not change
behavior based on other files defining DEBUG_TYPE, which means it cannot
define DEBUG_TYPE at all. This is actually better IMO as it forces folks
to define relevant DEBUG_TYPEs for their files. However, it requires all
files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't
already. I've updated all such files in LLVM and will do the same for
other upstream projects.

This still leaves one important change in how LLVM uses the DEBUG_TYPE
macro going forward: we need to only define the macro *after* header
files have been #include-ed. Previously, this wasn't possible because
Debug.h required the macro to be pre-defined. This commit removes that.
By defining DEBUG_TYPE after the includes two things are fixed:

- Header files that need to provide a DEBUG_TYPE for some inline code
  can do so by defining the macro before their inline code and undef-ing
  it afterward so the macro does not escape.

- We no longer have rampant ODR violations due to including headers with
  different DEBUG_TYPE definitions. This may be mostly an academic
  violation today, but with modules these types of violations are easy
  to check for and potentially very relevant.

Where necessary to suppor headers with DEBUG_TYPE, I have moved the
definitions below the includes in this commit. I plan to move the rest
of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big
enough.

The comments in Debug.h, which were hilariously out of date already,
have been updated to reflect the recommended practice going forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 22:55:11 +00:00