6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-12 16:29:31 +00:00
Code Issues Projects Releases Wiki Activity
84,413 Commits 39 Branches 0 Tags 277 MiB
cba48d8c05
Commit Graph

157 Commits

Author SHA1 Message Date
Anton Korobeynikov
ace53f2fbc Properly emit __chkstk call instead of __alloca on non-mingw windows targets. 
Patch by Cameron Esfahani!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
cdae7e8244 Add x86 CLMUL (Carry-less multiplication) cpu feature 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-23 01:17:51 +00:00
Eric Christopher
62f35a2c13 Have the X86 backend use Triple instead of a string and some enums. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-05 19:26:33 +00:00
Dan Gohman
4d3d6e1a0c FastISel doesn't yet handle callee-pop functions. 
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 18:43:40 +00:00
Evan Cheng
2bce5f4b56 Enable i16 to i32 promotion by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 08:30:49 +00:00
Evan Cheng
5528e7bcb1 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:47:12 +00:00
Eric Christopher
6d1cd1cd04 Separate out the AES-NI instructions from the SSE4.2 instructions. Add 
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 21:54:27 +00:00
Evan Cheng
48c58bb861 Nehalem unaligned memory access is fast. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-01 05:58:17 +00:00
Evan Cheng
bdc652bab8 Turning off post-ra scheduling for x86. It isn't a consistent win. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 06:55:42 +00:00
Chris Lattner
314a113184 add support for pentium class CPUs which do not have cmov, 
PR4841.  Patch by Craig Smith!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-14 18:31:44 +00:00
Mikhail Glushenkov
5d96eb8671 80-col violations/trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-28 22:54:30 +00:00
Anton Korobeynikov
ebb0c2b287 Setup correct data layout to match gcc's expectations on mingw32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95981 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 15:28:56 +00:00
Duncan Sands
990c4b87e3 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 08:30:46 +00:00
Duncan Sands
e2de606e0b Tweak commit 91745, which changed target data for both Mingw and Cygwin, 
to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 08:21:07 +00:00
David Greene
95eb2eeea6 Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 16:29:42 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Anton Korobeynikov
e9ec6ad1ba Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91745 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 02:04:23 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Dan Gohman
29cbade25a Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 23:18:13 +00:00
David Goodwin
87d21b92fc Allow target to specify regclass for which antideps will only be broken along the critical path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-13 19:52:48 +00:00
David Goodwin
c2e8a7e8d2 Fixed to address code review. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 00:15:47 +00:00
Chris Lattner
59a9178fbe indicate what the native integer types for the target are. 
Please verify.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 19:07:32 +00:00
Evan Cheng
c869d063d4 X86 needs critical path anti-dependency breaking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84931 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 05:57:35 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 23:19:17 +00:00
Evan Cheng
d36076e4a3 Turn on post-alloc scheduling for x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 19:57:27 +00:00
Evan Cheng
eb6e1daa43 Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84425 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 18:31:31 +00:00
Evan Cheng
ff89dcb06f -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 18:16:27 +00:00
Evan Cheng
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 21:06:15 +00:00
Evan Cheng
79f7400e4f Remove X86Subtarget::IsLinux. It's no longer being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84200 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:23:21 +00:00
Chris Lattner
a76e3fc131 rearrange X86ATTAsmPrinter::doFinalization, making a scan of 
the global variable list only happen for COFF targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82010 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 05:20:33 +00:00
Daniel Dunbar
848113833f Make these functions static and local. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80892 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 05:47:34 +00:00
Evan Cheng
d0da6ff3ad X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget. 
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80880 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-03 04:37:05 +00:00
Chris Lattner
700841617a Add support for modeling whether or not the processor has support for 
conditional moves as a subtarget feature.  This is the easy part of 
PR4841.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-02 05:53:04 +00:00
Chris Lattner
ce914b8f94 change the -x86-asm-syntax=intel/att flag to be in X86TAI 
instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 23:01:09 +00:00
Daniel Dunbar
3be03406c9 Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:11:08 +00:00
Chris Lattner
e2c920845a remove the now-dead TM argument to these methods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75276 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 21:00:45 +00:00
Chris Lattner
8097b65c43 make PIC vs DynamicNoPIC be explicit in PICStyles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 20:58:47 +00:00
Chris Lattner
3b67e9ba01 add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 20:47:30 +00:00
Chris Lattner
0d786dd954 simplify fast isel by using ClassifyGlobalReference. This 
elimiantes the last use of GVRequiresExtraLoad, so delete it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75244 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 07:48:51 +00:00
Chris Lattner
dfed413ef6 eliminate GVRequiresRegister, replacing it with predicates we 
need for other purposes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75243 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 07:38:24 +00:00
Chris Lattner
d392bd97c8 move some classification logic around. Now GVRequiresExtraLoad 
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75237 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 07:20:05 +00:00
Chris Lattner
ed0dca6a5d GVRequiresExtraLoad is now never used for calls, simplify it based on this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 05:52:02 +00:00
Chris Lattner
754b7650c2 actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code 
more complex and slow than just directly testing what we care about.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75231 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 05:48:03 +00:00
Chris Lattner
e6c07b52e7 There is only one case where GVRequiresExtraLoad returns true for calls: 
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75230 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 05:45:15 +00:00
Chris Lattner
04b304caf6 the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75229 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-10 05:37:11 +00:00
Chris Lattner
e4df756289 When in -static mode, force the PIC style to none. Doing this requires fixing 
code which conflated RIPRel PIC with x86-64.  Fix these to just check for X86-64
directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75092 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-09 03:15:51 +00:00
David Greene
640a0c1477 Fix a subtarget feature bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74428 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-29 16:51:01 +00:00
David Greene
343dadbb36 Add feature flags for AVX and FMA and fix some SSE4A feature flag 
initialization problems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-26 22:46:54 +00:00
Chris Lattner
aecaa1f143 cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73836 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-21 01:27:55 +00:00
Stefanus Du Toit
8cf5ab153d Update CPU capabilities for AMD machines 
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-26 21:04:35 +00:00
Anton Korobeynikov
41a024385f Propagate CPU string out of SubtargetFeatures 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-23 19:50:50 +00:00
Evan Cheng
d7f666a869 Try again. Allow call to immediate address for ELF or when in static relocation mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-20 04:53:57 +00:00
Dan Gohman
d68a07650c Tidy up #includes, deleting a bunch of unnecessary #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-05 17:59:02 +00:00
Evan Cheng
ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-02 05:35:45 +00:00
Dan Gohman
8749b61178 Add initial support for back-scheduling address computations, 
especially in the case of addresses computed from loop induction
variables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-16 03:35:01 +00:00
Dale Johannesen
368eb2b22d Forgot a file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60609 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-05 21:55:35 +00:00
Duncan Sands
f9a67a8943 Fix build with gcc-4.4: it doesn't like PICStyle 
being both a namespace and a variable name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60208 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-28 09:29:37 +00:00
Bill Wendling
6e08738d4b Just don't transform this memset into "bzero" if no-builtin is specified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 22:05:33 +00:00
Bill Wendling
6f287b22d2 Add the new `-no-builtin' flag. This flag is meant to mimic the GCC 
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 21:22:07 +00:00
Dan Gohman
600bf16cf7 Use a dedicated IsLinux flag instead of an ELFLinux TargetType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 16:11:31 +00:00
Dan Gohman
a779a9899a Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-05-05 00:28:39 +00:00
Evan Cheng
43b7ca15a3 Re-enable SSE4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49158 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-03 08:53:29 +00:00
Evan Cheng
b4e56d4a2b Temporarily disabling SSE4 until we fix the encoding issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49129 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-03 04:49:54 +00:00
Dan Gohman
68d599df37 Speculatively micro-optimize memory-zeroing calls on Darwin 10. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49048 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-04-01 20:38:36 +00:00
Anton Korobeynikov
1a979d9eab Add convenient helper for win64 check. Simplify things slightly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48691 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-22 20:57:27 +00:00
Evan Cheng
add251754c Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47002 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-12 07:59:55 +00:00
Evan Cheng
be3bf42331 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-07 08:53:49 +00:00
Nate Begeman
63ec90a6a8 SSE 4.1 Intrinsics and detection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-03 07:18:54 +00:00
Chris Lattner
7ad92d81e2 darwin9 and above support aligned common symbols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45494 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-02 19:44:55 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Rafael Espindola
fc05f402ea Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-10-31 11:52:06 +00:00
Rafael Espindola
588af2fb99 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41768 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-07 14:52:14 +00:00
Evan Cheng
29d62bebd9 Mac OS X X86-64 ABI is same as the standard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41700 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-09-04 16:44:41 +00:00
Rafael Espindola
7240ae3cac Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41642 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-31 12:23:58 +00:00
Dale Johannesen
9989a65693 Replace 4-line function with 10-line version per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40881 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 22:10:35 +00:00
Dale Johannesen
27f92be8b7 Move lengthy conditional down 1 level per review comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40878 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-06 21:48:35 +00:00
Evan Cheng
f6844ca0e4 Mac OS X X86-64 low 4G address not available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-08-01 23:45:51 +00:00
Bill Wendling
bb1ee05253 Add support for our first SSSE3 instruction "pmulhrsw". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-10 22:10:25 +00:00
Chris Lattner
26aa785942 document some subtlety 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33257 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-16 17:51:40 +00:00
Bill Wendling
cb9009993b Instead of yet another enum indicating the "assembly language flavor", 
just use the one that's in the subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33255 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-16 09:29:17 +00:00
Anton Korobeynikov
7f70559bc4 * PIC codegen for X86/Linux has been implemented 
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-12 19:20:47 +00:00
Anton Korobeynikov
317848f4a1 Really big cleanup. 
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-03 11:43:14 +00:00
Anton Korobeynikov
2b2bc68884 Refactored JIT codegen for mingw32. Now we're using standart relocation 
type for distinguish JIT & non-JIT instead of "dirty" hacks :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32745 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-22 22:29:05 +00:00
Anton Korobeynikov
15fccf1d93 Fixed dllimported symbols support during JIT'ing. JIT on mingw32 
platform should be more or less workable. At least, sim is running fine
under lli :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32711 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-12-20 01:03:20 +00:00
Anton Korobeynikov
7784ebc239 Factor out GVRequiresExtraLoad() from .h to .cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32048 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-30 22:42:55 +00:00
Anton Korobeynikov
12c49af81e Refactored *GVRequiresExtraLoad() to Subtarget method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31887 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-21 00:01:06 +00:00
Evan Cheng
751c0e12db Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30985 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-16 21:00:37 +00:00
Evan Cheng
a26eb5e1a7 Still need to support -mcpu=<> or cross compilation will fail. Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 09:17:41 +00:00
Evan Cheng
abc346ceda Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-06 08:21:07 +00:00
Anton Korobeynikov
b74ed07bfd Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30374 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-14 18:23:27 +00:00
Evan Cheng
25ab690a43 Committing X86-64 support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-08 06:48:29 +00:00
Chris Lattner
2dd538c2d2 add a new value for the command line optn 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30165 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 22:32:28 +00:00
Jim Laskey
05a059d5d8 Make the x86 asm flavor part of the subtarget info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-07 12:23:47 +00:00
Chris Lattner
dd842e12e1 Add accessor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30080 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-04 04:08:58 +00:00
Evan Cheng
7ccced634a x86 / Darwin PIC support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-18 00:15:05 +00:00
Evan Cheng
18a8452f3d A bit more memset / memcpy optimization. 
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-16 00:21:07 +00:00
Chris Lattner
259e97cc72 * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 19:43:35 +00:00
Evan Cheng
559806f575 x86 CPU detection and proper subtarget support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 08:10:46 +00:00
Evan Cheng
97c7fc351e Added preliminary x86 subtarget support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25645 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 09:53:06 +00:00