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cd59dc5e81
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2911 Commits

Author SHA1 Message Date
Jim Grosbach
cd59dc5e81 add ARM cmd line option to force always using virtual base regs when possible. 
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 18:04:52 +00:00
Bill Wendling
5e7044bd0e Add comments for what the condition code symbols mean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:11:30 +00:00
Eric Christopher
882d62e2db Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:52 +00:00
Eric Christopher
2012c7bb7b Fix the opcode and the operands for the load instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:04 +00:00
Eric Christopher
f06f309002 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:50:47 +00:00
Eric Christopher
cb0b04ba6f Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:07:24 +00:00
Eric Christopher
1dfb4d31e0 Don't need the extra register here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:28:04 +00:00
Eric Christopher
8654c71e56 Add some more "get address into register" code and a more TODOs/FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:14:31 +00:00
Eric Christopher
7fe55b739c Add an ARMFunctionInfo member and use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 22:32:45 +00:00
Eric Christopher
8300712c1e Start getting ARM loads/address computation going. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 21:44:12 +00:00
Bob Wilson
b31a11b466 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and 
zero-extend operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 04:54:02 +00:00
Eric Christopher
f762fbe4fa Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:36:24 +00:00
Eric Christopher
cb59229a4a Add a couple of random comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:20:31 +00:00
Jim Grosbach
e2f556933e Better handling of offsets on frame index references. rdar://8277890 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 23:52:25 +00:00
Jim Grosbach
74d7b0af58 Add Thumb1 support for virtual frame indices. 
rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:52:13 +00:00
Eric Christopher
979e0a1414 Silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 15:35:27 +00:00
Eric Christopher
456144eb14 Add an AddOptionalDefs method and use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 00:37:05 +00:00
Bill Wendling
f0e132c385 Add the "isCompare" attribute to the defm instead of each individual instr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 00:05:48 +00:00
Eric Christopher
d96b02b3d6 Remove extra header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 23:38:16 +00:00
Jim Grosbach
2b1e202e1c Enable ARM base register reuse to local stack slot allocation. Whenever a new 
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 22:44:49 +00:00
Bill Wendling
ad422718f9 Minor simplification. Gets rid of a needless temporary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 21:32:07 +00:00
Jim Grosbach
74d803a58c Add hook for re-using virtual base registers for local stack slot access. 
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 17:57:37 +00:00
Bob Wilson
2003bcfbd2 Expand ZERO_EXTEND operations for NEON vector types. 
Testcase from Nick Lewycky.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 01:45:52 +00:00
Jim Grosbach
dc140c6e7b Add materialization of virtual base registers for frame indices allocated into 
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 22:41:55 +00:00
Jakob Stoklund Olesen
00d3dda86f Don't call tablegen'ed Predicate_* functions in the ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 20:39:04 +00:00
Jim Grosbach
c5ed0134a7 80 column cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 18:39:16 +00:00
Jim Grosbach
8708ead5a4 Add hook to examine an instruction referencing a frame index to determine 
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 18:13:53 +00:00
Jim Grosbach
3edb904927 explicitly handle no-op cases for clarity. Fixes clang warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 18:00:41 +00:00
Bob Wilson
f955f290c9 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:23:19 +00:00
Chris Lattner
23e70ebf35 fix emacs language spec's, patch by Edmund Grimley-Evans! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 16:20:04 +00:00
Bob Wilson
7aaf5bf3db Allow more cases of undef shuffle indices and add tests for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 05:54:34 +00:00
Eric Christopher
0fe7d54732 Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:25:29 +00:00
Eric Christopher
038fea5e30 Make arm fast-isel possible to enable via command line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 00:46:57 +00:00
Bob Wilson
ca5e47d3f8 Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 23:37:17 +00:00
Bob Wilson
dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 22:26:55 +00:00
Bob Wilson
22f5dc79c0 Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 18:27:34 +00:00
Bob Wilson
45cdd7fd61 Remove unused code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-16 17:06:03 +00:00
Bob Wilson
136e491280 T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-14 03:18:29 +00:00
Bob Wilson
20d8e4e7aa Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 23:24:25 +00:00
Bob Wilson
703af3ab12 Temporarily disable tail calls on ARM to work around some linker problems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 22:43:33 +00:00
Bob Wilson
38aa2871fc Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 21:48:10 +00:00
Bob Wilson
6daf2a254b Refactor the code for disassembling Thumb2 saturate instructions along the 
same lines as the change I made for ARM saturate instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111029 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 19:04:21 +00:00
Johnny Chen
1adc40cac3 Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:46:17 +00:00
Evan Cheng
719510a178 Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:30:05 +00:00
Johnny Chen
270159fcc2 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 01:40:54 +00:00
Daniel Dunbar
f1e29d4c21 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:38 +00:00
Daniel Dunbar
4f98f83459 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 00:55:32 +00:00
Johnny Chen
7def14f40f Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:35:12 +00:00
Bob Wilson
eaf1c98a7c Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 23:10:46 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 15:44:15 +00:00