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14043 Commits

Author SHA1 Message Date
Andrew Trick
7c12837916 Lit option for ignoring stderr output. 
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 17:42:33 +00:00
Roman Divacky
0aaa9195b5 Set CR1EQ only when lowering vararg floating arguments (not any vararg 
arguments as before), unset CR1EQ otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138802 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 17:04:16 +00:00
Craig Topper
3daa5c29d4 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 07:09:35 +00:00
Evan Cheng
342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 01:34:54 +00:00
Owen Anderson
694e0ffb8a Add missing encoding information for some of the GPR<->FP register moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:15:25 +00:00
Jim Grosbach
abd3f60859 Remove redundant tests from XFAIL'ed test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:04:04 +00:00
Jim Grosbach
a01e12499f Thumb2 assembly parsing and encoding support for ADC(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138778 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:01:38 +00:00
Jim Grosbach
056cb4c0f6 Remove test file. Superceded by other more exhaustive tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138777 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 23:00:19 +00:00
Jim Grosbach
f8e1e3e729 Thumb2 parsing and encoding for IT blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:24:09 +00:00
Kevin Enderby
fff64ca9cf Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:06:28 +00:00
Eli Friedman
f3704769bb Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138768 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 21:15:46 +00:00
Bill Wendling
6af6824eb4 Update tests to new EH model. Add landingpad instructions to landing pads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 20:39:23 +00:00
Nadav Rotem
89879ec76b Fixes following the CR by Chris and Duncan: 
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138756 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 19:58:36 +00:00
Owen Anderson
0da10cf44d Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 19:36:44 +00:00
Owen Anderson
50e2dedb51 Add testcase for r138746. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 18:02:40 +00:00
Owen Anderson
63553c77cd Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 17:17:09 +00:00
Duncan Sands
fd9c4f76f4 Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-28 13:17:22 +00:00
Nadav Rotem
be6ceb6ebc Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-28 11:51:08 +00:00
Andrew Trick
d326d3b3ef Reverted r138652, valgrind doesn't understand obj:*/tblgen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 06:17:30 +00:00
Bill Wendling
df77a71790 Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If 
things to disasterously over night, this can be reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 06:11:03 +00:00
Bill Wendling
234e43a888 Update to new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 04:53:41 +00:00
Bill Wendling
f2cf25b212 Cannot have an llvm.eh.exception call in a non-landing pad block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 04:53:28 +00:00
Andrew Trick
0005cc7a0a Excluding ARM JIT tests until someone can fix this compilation path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:39:30 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Owen Anderson
d7568e1c35 Correct encoding of BL with immediate offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 22:54:51 +00:00
Eli Friedman
43f51aeca8 Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:21:21 +00:00
Bill Wendling
1f4a32f5ac Revert r138606 until LowerInvoke has been converted to the new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 21:11:23 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:43:14 +00:00
Andrew Trick
ae5ea6cab0 valgrind: Always suppress tblgen leaks. 
I'll clean up the rest of the XFAIL: vg_leak lines if this works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:41:20 +00:00
Bill Wendling
2b18881185 Don't sink landingpad instructions during ind-var simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138651 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:40:15 +00:00
Andrew Trick
6ca06cd8a8 Use %% for literals in RUN lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:09:48 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 18:09:22 +00:00
Benjamin Kramer
06a531ff63 We don't care if TableGen leaks memory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 17:00:30 +00:00
Owen Anderson
5a18f20dab Add a testcase for r138625. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 06:45:08 +00:00
Craig Topper
8fd13b6de5 Fix disassembling of VCVTSD2SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 04:49:29 +00:00
Eli Friedman
069e2ed794 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 02:59:24 +00:00
Benjamin Kramer
98d6d2372f SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. 
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.

This shrinks the size of a Release clang by 16k on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 01:22:29 +00:00
Bill Wendling
1a9a2d0d6b Update to the new EH scheme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 23:48:37 +00:00
Bruno Cardoso Lopes
6292eceea0 Add support for AVX 256-bit version of MOVDDUP! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 21:40:37 +00:00
Owen Anderson
99906830e8 Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 18:30:18 +00:00
Andrew Trick
b9ca5124f8 ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 17:50:53 +00:00
Craig Topper
113061d39b Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 07:42:00 +00:00
Craig Topper
ea03659d23 Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 06:57:46 +00:00
Bill Wendling
8b6af8a2a9 LSR wants to split the landing pad's critical edge. Let it do it, but use the 
proper function to do it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 05:55:40 +00:00
Bruno Cardoso Lopes
07b7f672a0 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 02:58:26 +00:00
Bill Wendling
76cf779bb8 Update tests to the newest EH syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138541 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 01:30:18 +00:00
Bill Wendling
c5fb9d86b0 Add feature test for the new exception handling stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 01:19:13 +00:00
Eli Friedman
f8f90f0174 Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138505 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:33:28 +00:00
Evan Cheng
5fbe5e783e Some autoconf tests use module level inline asm to test compiler's handling of 
.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:31:37 +00:00
Jim Grosbach
070260cb29 Update tests for 138501. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 22:30:18 +00:00