Commit Graph

16284 Commits

Author SHA1 Message Date
Cameron Esfahani
d7b8d91d4a Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 10:31:30 +00:00
Bob Wilson
7d24705f65 Change register allocation order for ARM VFP and NEON registers to put the
callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
Chris Lattner
d043529b34 fix a subtle bug I introduced in my refactoring, where we stopped preferring
the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 05:12:14 +00:00
Chris Lattner
15df55d8c2 reapply: Use the new TB_NOT_REVERSABLE flag instead of special
reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:57:25 +00:00
Chris Lattner
99ae6659da reapply the patch reverted in r116033:
"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 03:54:52 +00:00
Daniel Dunbar
b88b00ba2b Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
'add'", which seems to have broken just about everything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:32 +00:00
Daniel Dunbar
b38109fc2d Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:29 +00:00
Daniel Dunbar
32f0cdba30 Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 02:07:26 +00:00
Eric Christopher
7a56f33583 Move to thumb2 loads, fixes a problem with incoming registers
as thumb1.

Fixes lencod.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:13:17 +00:00
Chris Lattner
cd3167b281 reimplement the second half of the or/add optimization. We should now
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 01:05:10 +00:00
Jim Grosbach
58f38bfa24 Enable binary encoding of some simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Chris Lattner
05e27c5786 Use the new TB_NOT_REVERSABLE flag instead of special
casing FsMOVAPDrr/FsMOVAPSrr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116016 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:03:02 +00:00
Chris Lattner
a228376185 simplify some map operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:57:02 +00:00
Chris Lattner
122e2ea043 Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies.  However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).

While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA.  This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.

This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20

the add r/i cases are coming next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116007 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:36:18 +00:00
Evan Cheng
344d9db970 Code refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:12:15 +00:00
Chris Lattner
45a1cb26a3 Reduce casting in various tables by defining the table
with the right types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 23:08:41 +00:00
Chris Lattner
afcd543a55 simplify code: don't build up vector only to assert it is empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:26:19 +00:00
Owen Anderson
ce665bd2e2 Now with fewer extraneous semicolons!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:25:06 +00:00
Jim Grosbach
d6d4b42ba4 Trivial MC code emitter shell. No instruction forms actually handled yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b Include the auto-generated bits for machine encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:57:55 +00:00
Eric Christopher
df1f5a924e Remember to promote load/store types for stack to register size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:40:18 +00:00
Chris Lattner
9649e9acdd convert test to use the existing classes that the multipatterns
use.  Since TEST is completely different than all other binops,
don't define a multipattern for it.

This completes factorization of binops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:31:03 +00:00
Chris Lattner
00e94baf4e convert cmp to use a multipattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:56:25 +00:00
Evan Cheng
835580fc3a Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:50:20 +00:00
Jim Grosbach
ae93ed1dd7 ARM instruction don't have instruction prefixes, so remove the helper functions
for them from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:41:30 +00:00
Chris Lattner
9e94000c16 reduce redundancy between pattern copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:14:23 +00:00
Chris Lattner
a2b8b16c7e the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:06:24 +00:00
Owen Anderson
154c5c46fc Improve comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115966 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:05:18 +00:00
Chris Lattner
a3208e122c convert adc/sbb to a multipattern. Because the adde/sube nodes
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.

This could be handled through better instantiation support in tblgen,
but it isn't meta enough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:01:55 +00:00
Owen Anderson
9966306aa7 Add initialization routines for Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:50:11 +00:00
Jakob Stoklund Olesen
8456c4f957 Fix obvious mistake pointed out by Michael Spencer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 18:47:10 +00:00
Kalle Raiskila
218c98c284 Add the missing cases to the type->registerclass conversion function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:32:42 +00:00
Kalle Raiskila
8a52fa674b Implement two virtual functions in SPUTargetLowering.
Before the implementation of isLegalAddressingMode, some rare cases 
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a 
bad TargetLowering, or if the bug is elsewhere and this patch just 
hides it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:24:35 +00:00
Eric Christopher
ee56ea6243 Use the correct register class for load instructions - fixes
compilation of MultiSource/Benchmarks/Bullet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:50:44 +00:00
Eric Christopher
5d18d92aad Use the correct register class here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:39:19 +00:00
Eric Christopher
338c253d7e Use the thumb2 conditional move instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:31:49 +00:00
Eric Christopher
1107734e22 Remove in-progress assertion, add TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 05:14:08 +00:00
Evan Cheng
5a50ceeaea Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:50:48 +00:00
Chris Lattner
b046810fe4 add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
allowing us to convert ADD over.  deletes 160 lines of .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:37:01 +00:00
Chris Lattner
521ff704a1 Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:26:27 +00:00
Chris Lattner
4b181c87de Convert 'and' to single instance of a multipattern
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 01:10:20 +00:00
Jim Grosbach
a4257162be Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:53:56 +00:00
Chris Lattner
511c686f76 add a new BinOpAI class to represent the immediate form that directly acts on EAX.
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:43:39 +00:00
Jim Grosbach
3bbdcea49a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:42:42 +00:00
Chris Lattner
1bb9adae4c add a bunch of classes for other common patterns.
As usual, no change in generated .inc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080 Define a new BinOpRI8 class and use it to define the imm8 versions of and.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6 Constrain the offset register to a *_NOSP register class when inserting LEA
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf add the pattern operator to match to X86TypeInfo, use this to
convert AND64ri32 to use BinOpRI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0 Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
This function looks like it is about ready to be generated by TebleGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:56:46 +00:00