Commit Graph

103977 Commits

Author SHA1 Message Date
Tim Northover
e072ed71c8 ARM64: separate load/store operands to simplify assembler
This changes ARM64 to use separate operands for each component of an
address, and look for separate '[', '$Rn, ..., ']' tokens when
parsing.

This allows us to do away with quite a bit of special C++ code to
handle monolithic "addressing modes" in the MC components. The more
incremental matching of the assembler operands also allows for better
diagnostics when LLVM is presented with invalid input.

Most of the complexity here is with the register-offset instructions,
which were extremely dodgy beforehand: even when the instruction used
wM, LLVM's model had xM as an operand. We papered over this
discrepancy before, but that approach doesn't work now so I split them
into separate X and W variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:56:09 +00:00
Daniel Sanders
b08e03806f [mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6
Summary:
* Split into two functions, one to test each struct.
* R0 and R2 must be defined by an lw with a %got reference to the correct
  symbol.
* Test for $4 (first argument) where appropriate instead of accepting any
  register.
* Test that the two lbu's are correctly combined into $4

Depends on D3844

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3845

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:55:04 +00:00
Daniel Sanders
98eba92334 [mips] Change lwl and lwr in inlineasm_constraint.ll to lw
Summary:
lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test
is to check that the '$1' expands to '0($x)' rather than to test something related
to the lwl or lwr instructions so we can simply switch to lw.

Depends on D3842

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:51:06 +00:00
Daniel Sanders
8afb08e5b5 [mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.

No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.

Depends on D3842

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:46:58 +00:00
Bradley Smith
00011c71f9 Extend sys::getHostCPUFeatures to work on AArch64 platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209420 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:44:34 +00:00
Daniel Sanders
e3ece90f24 [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:42:31 +00:00
Daniel Sanders
5f45ba140e [mips][mips64r6] Test that paired single instructions are invalid
Summary:
These emit the 'unknown instruction' instead of the correct error
because they have not been implemented in LLVM for any MIPS ISA.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:37:38 +00:00
Daniel Sanders
c96096cc0f [mips][mips64r6] Add b[on]vc
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
  * Also made non-functional change to DecodeBranchTarget and
    DecodeBranchTargetMM to keep implementation style consistent between
    them.
* Difficult encodings are handled by a custom decode method on the most
  general encoding in the group. This method will convert the MCInst to a
  different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:23:21 +00:00
Tim Northover
2447dcc2e8 ARM64: assert if we see i64 -> i64 extend in the DAG.
Should be no change in behaviour, but it makes the intended
functionality a bit clearer and means we only have to reason about
real extend operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209409 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 07:41:37 +00:00
Tim Northover
de9e4c88c8 AArch64/ARM64: enable more AArch64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 07:40:55 +00:00
Saleem Abdulrasool
327edb432a MC: initialise MCAsmParser variable
Properly initialise HadError to false during construction.  Detected as
use-of-uninitialised variable by MSan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 06:02:59 +00:00
Eric Christopher
9c553cfe79 Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209391 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 05:33:03 +00:00
Saleem Abdulrasool
71ce2118bb ARM: introduce llvm.arm.undefined intrinsic
This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU).  This permits the operating system to implement custom behaviour on
this trap.  The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend.  This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209390 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 04:46:46 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 03:20:30 +00:00
Saleem Abdulrasool
f4f930c795 MC: formalise some assertions into proper errors
Now that clang can be used as an assembler via the IAS, invalid assembler inputs
would cause the assertions to trigger.  Although we cannot recover from the
errors here, nor provide caret diagnostics, attempt to handle them slightly more
gracefully by reporting a fatal error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 02:18:10 +00:00
Eric Christopher
424bbbbbbc Override runOnMachineFunction for ARMISelDAGToDAG so that we can
reset the subtarget on each function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209386 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 02:00:27 +00:00
Eric Christopher
c5f6f15fe5 Override runOnMachineFunction for X86ISelDAGToDAG so that we can
reset the subtarget on each function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209384 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:53:26 +00:00
Eric Christopher
26bbeece29 Avoid using subtarget features when adding X86 specific passes to
the pass pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209382 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:46:02 +00:00
Eric Christopher
1e264de205 Remove extra local variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:45:59 +00:00
Eric Christopher
42854e57a9 Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to make
it obvious that it's a target specific pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209380 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:45:57 +00:00
Eric Christopher
4551b0a800 Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209377 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:21:44 +00:00
Eric Christopher
6ccae2df5b Avoid using subtarget features when initializing the pass pipeline
on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:21:35 +00:00
Eric Christopher
58d9172bb4 Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.
This required updating the generated functions and TD file accordingly
to be pointers rather than const references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209375 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:07:24 +00:00
Eric Christopher
162180cba5 Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209374 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:07:21 +00:00
Eric Christopher
14fb9b6069 Sort includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209373 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 01:07:18 +00:00
David Blaikie
b1a3b17e78 DebugInfo: Simplify dead variable collection slightly.
constructSubprogramDIE was already called for every subprogram in every
CU when the module was started - there's no need to call it again at
module finalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209372 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 00:48:36 +00:00
Andrew Trick
facca6e3f3 Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.
This has to do with the trip count computation for loops with multiple
exits, which is quite subtle. Most passes just ask for a single trip
count number, so we must be conservative assuming any exit could be
taken.  Normally, we rely on the "exact" trip count, which was
correctly given as "unknown". However, SCEV also gives a "max"
back-edge taken count. The loops max BE taken count is conservatively
a maximum over the max of each exit's non-exiting iterations
count. Note that some exit tests can be skipped so the max loop
back-edge taken count can actually exceed the max non-exiting
iterations for some exits. However, when we know the loop *latch*
cannot be skipped, we can directly use its max taken count
disregarding other exits. I previously took the minimum here without
checking whether the other exit could be skipped. The correct, and
simpler thing to do here is just to directly use the loop latch's max
non-exiting iterations as the loops max back-edge count.

In the problematic test case, the first loop exit had a max of zero
non-exiting iterations, but could be skipped. The loop latch was known
not to be skipped but had max of one non-exiting iteration. We
incorrectly claimed the loop back-edge could be taken zero times, when
it is actually taken one time.

Fixes Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count.
Loop %for.body.i: max backedge-taken count is 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209358 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 00:37:03 +00:00
Eli Bendersky
107db21c2b Similar to bitcast, treat addrspacecast as a foldable operand.
Added a test sink-addrspacecast.ll to verify this change.

Patch by Jingyue Wu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 00:02:52 +00:00
Eric Christopher
a2f371b8eb Fix compilation issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209342 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:51:57 +00:00
Eric Christopher
189fe78e2f Make early if conversion dependent upon the subtarget and add
a subtarget hook to enable. Unconditionally add to the pass pipeline
for targets that might want to use it. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209340 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:40:26 +00:00
Eric Christopher
595bdb7e8b Group the scheduling functions together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:40:18 +00:00
David Blaikie
8a0240ddf2 Revert "DebugInfo: Don't put fission type units in comdat sections."
This reverts commit r208930, r208933, and r208975.

It seems not all fission consumers are ready to handle this behavior.
Reverting until tools are brought up to spec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:27:41 +00:00
Saleem Abdulrasool
cba7ac7bda MC: correct IMAGE_REL_ARM_MOV32T relocation emission
This corrects the emission of IMAGE_REL_ARM_MOV32T relocations.  Previously, we
were avoiding the high portion of the relocation too early.  If there was a
section-relative relocation with an offset greater than 16-bits (65535), you
would end up truncating the high order bits of the offset.  Allow the current
relocation representation to flow through out the MC layer to the object writer.
Use the new ability to restrict recorded relocations to avoid emitting the
relocation into the final object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:17:56 +00:00
Saleem Abdulrasool
159ccc8f51 MC: introduce ability to restrict recorded relocations
Add support to allow a target specific COFF object writer to restrict the
recorded resolutions in the emitted object files.  This is motivated by the need
in Windows on ARM, where an intermediate relocation needs to be prevented from
being emitted in the object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:17:50 +00:00
David Blaikie
111bad385a DebugInfo: Use the SPMap to find the parent CU of inlined functions as they may not be in the current CU
Committed in r209178 then reverted in r209251 due to LTO breakage,
here's a proper fix for the case of the missing subprogram DIE. The DIEs
were there, just in other compile units. Using the SPMap we can find the
right compile unit to search for and produce cross-unit references to
describe this kind of inlining.

One existing test case needed to be updated because it had a function
that wasn't in the CU's subprogram list, so it didn't appear in the
SPMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209335 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:14:12 +00:00
Matt Arsenault
afd1747bbc R600: Add comment describing problems with LowerConstantInitializer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:59:17 +00:00
Matt Arsenault
bd124c85ef R600: Partially fix constant initializers for structs and vectors.
This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:42 +00:00
Matt Arsenault
713096fb68 R600: Add failing testcases for constant initializers.
Constant initializers involving illegal types hit an assertion.

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:38 +00:00
Eric Christopher
5fe59a2e10 Remove getTargetLowering from TargetPassConfig as the target lowering
can change depending upon subtarget/subtarget features for a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209329 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:07 +00:00
Eric Christopher
9bfc3f592d Remove unused member variable from hexagon pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209328 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:42:02 +00:00
David Blaikie
30436451e2 DebugInfo: Ensure concrete out of line variables from inlined functions reference their abstract origins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:41:17 +00:00
Quentin Colombet
fd0096a42c [X86] Fix a bug in the lowering of BLENDI introduced in r209043.
ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the
second argument.
On the other hand, BLENDI uses 0 to identify the first argument and 1 to
identify the second argument.
Fix the generation of the blend mask to account for this difference.

The bug did not show up with r209043, because we were not checking for the
actual arguments of the blend instruction!
This commit also fixes the test cases.

Note: The same mask works for the BLENDr variant because the arguments are
swapped during instruction selection (see the BLENDXXrr patterns).

<rdar://problem/16975435>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209324 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 22:00:39 +00:00
Eric Christopher
d1b5bdaebd Move MCOptions that aren't shared between programs into their specific
program and have them initialize the MCOptions struct explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209321 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 21:05:09 +00:00
Eric Christopher
9a37986328 Make a couple of command lines static and remove an unnecessary
initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 21:05:05 +00:00
David Blaikie
c10a1edf3f DebugInfo: Simplify subprogram declaration creation/references and accidentally refix PR11300.
Also simplifies the linkage name handling a little too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209311 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 18:04:33 +00:00
Matt Arsenault
49323774b4 Use cast<> instead of unchecked dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209310 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 18:03:59 +00:00
Saleem Abdulrasool
5dd4b9f43b MC: loosen an overzealous assertion
Permit active macro expansions when terminating the assembler if there were
errors during the expansion.  This would only trigger on invalid input when
built with assertions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209309 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 17:53:18 +00:00
Greg Fitzgerald
03b003b1cb Use llvm-lit if LLVM source tree is unavailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209308 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 16:44:03 +00:00
Dave Estes
c12c3d0753 Test comment commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209306 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 16:19:51 +00:00
Daniel Sanders
820861536c [mips][mips64r6] Add bc[12](eq|ne)z
Summary: Depends on D3691

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 12:56:39 +00:00