Commit Graph

48535 Commits

Author SHA1 Message Date
Owen Anderson
e0a03143df Fix test failures caused by my so_reg refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135785 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:30:30 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:13:31 +00:00
Jim Grosbach
7931df3d74 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:06:01 +00:00
Jim Grosbach
0fdf6ccf17 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:04:10 +00:00
Jim Grosbach
0632247818 Thumb assembly support for SETEND instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 17:52:23 +00:00
Jim Grosbach
53a89d6f38 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 17:46:13 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 17:44:50 +00:00
Jim Grosbach
6c1bb77992 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 16:59:04 +00:00
Jay Foad
b4263a6ff4 Fix more MSVC warnings caused by a cases I missed when converting
ConstantExpr::getGetElementPtr to use ArrayRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135762 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 08:52:50 +00:00
Jay Foad
0a2a60ace9 Convert IRBuilder::CreateGEP and IRBuilder::CreateInBoundsGEP to use
ArrayRef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 08:16:57 +00:00
Chandler Carruth
48ac8e9be7 Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs.
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.

Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 08:16:53 +00:00
Jay Foad
8908ff207d Fix an MSVC warning, caused by a case I missed when converting
ConstantExpr::getGetElementPtr to use ArrayRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 07:54:01 +00:00
Chandler Carruth
4039313b4c Move the registered target printing in version strings completely out of
the Support library. Now its part of the TargetRegistry, and the three
commands that care about this explicitly register this extra bit of
version information.

The set of commands which care was computed by intersecting those which
use the Support library's version string printing and those that
initialize all the registered targets in a way that produces
a meaningful list. The only odd ball out is that 'clang -cc1as -version'
no longer prints the registered targets. I don't think anyone is really
interested in that (especially as the fact that llvm-mc does so is under
a FIXME), but if someone really does want this back I'll happily apply
the same patch there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 07:50:48 +00:00
Chandler Carruth
077c408717 Move the logic for printing the registered targets into a static
function on the TargetRegistry. Also clean it up and use the modern LLVM
utility libraries available instead of rolling a few things manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 07:50:44 +00:00
Chandler Carruth
6d51d26a24 Add an extension point to the CommandLine library where clients can
register extra version information to be printed. This is designed to
allow those tools which link in various targets to also print those
registered targets under --version.

Currently this printing logic is embedded into the Support library
directly; a huge layering violation. This is the first step to hoisting
it out into the tools without adding lots of duplicated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135755 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 07:50:40 +00:00
NAKAMURA Takumi
12b2772578 lib/Support/Triple.cpp: Recognize "-march=ppc32" to llc properly, as quick hack.
FIXME: There is an inconsistency. llvm::Triple does not understand "ppc32" and PowerPC/TargetInfo holds "ppc32".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 04:02:22 +00:00
Jakub Staszak
23f34f1c22 Allow getBlockFreq to return 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 02:24:57 +00:00
Benjamin Kramer
558cc5a914 GCC complains about the angle of this line.
Remove the escaped newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 01:02:57 +00:00
Jakub Staszak
4e2710c266 Revert patch which broke some IfConversion tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:55:15 +00:00
Jakub Staszak
6b598748b1 Fix typo in #include which revealed in the case-sensitive filesystem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:39:00 +00:00
Bruno Cardoso Lopes
c41e593509 Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:10 +00:00
Bruno Cardoso Lopes
6683efb4cd -Inspected a AVX code block added by someone in early Feb. This was never used
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
74dad551d8 Add a DAGCombine for transforming 128->256 casts into a simple
vxorps + vinsertf128 pair of instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:00 +00:00
Bruno Cardoso Lopes
d088834fb9 Introduce a new function to lower 256-bit vectors which are not
direclty supported and should be promoted and handled by smaller
shuffles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:14:56 +00:00
Bruno Cardoso Lopes
589b897a31 Rename function to be more specific and be more strict about its usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:14:53 +00:00
Jakub Staszak
8592d903e1 Use MachineBranchProbabilityInfo instead of MachineLoopInfo in IfConversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:48:55 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:38:37 +00:00
Dan Gohman
856e13ddac Fix MergeInVectorType to check for vector types with the same alloc
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:30:09 +00:00
Jim Grosbach
7c6e42e927 ARM Asm parser range checking for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:26:25 +00:00
Jakub Staszak
9d81c97c8a Add missing getAnalysisUsage in MachineBlockFrequency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:59:09 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:37:43 +00:00
Jim Grosbach
43d3b31cda Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 21:26:05 +00:00
Nicolas Geoffray
a056d20167 Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 20:59:21 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 19:57:11 +00:00
Oscar Fuentes
45e11c7cc7 Fix CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135698 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 19:10:57 +00:00
Owen Anderson
92a202213b Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 18:54:16 +00:00
Andrew Trick
a305fe7545 Cleanup: make std::pair usage slightly less indecipherable without actually naming variables!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 17:37:39 +00:00
Jim Grosbach
f6c0525d42 ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 17:23:04 +00:00
Bruno Cardoso Lopes
dca6cdd6a1 Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 16:28:51 +00:00
Jay Foad
4b5e207bf2 Make better use of ConstantExpr::getGetElementPtr's InBounds parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 15:15:37 +00:00
Jay Foad
dab3d29605 Convert ConstantExpr::getGetElementPtr and
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135673 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 14:31:17 +00:00
Chris Lattner
c30a38f34b move tier out of an anonymous namespace, it doesn't make sense
to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 06:21:31 +00:00
Bruno Cardoso Lopes
dbd4fe2b0a - Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
Bruno Cardoso Lopes
9283b668a1 Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:42 +00:00
Bruno Cardoso Lopes
0e87805074 Add aditional patterns for vextractf128 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:39 +00:00
Bruno Cardoso Lopes
df0e03ceb8 Add aditional patterns for vinsertf128 instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:36 +00:00
Bruno Cardoso Lopes
11bbb2003a Add v16i16 type to VR256 class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:33 +00:00
Bruno Cardoso Lopes
bca4781b61 Move code around. No functionality changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:30 +00:00