6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-11 23:05:31 +00:00
Code Issues Projects Releases Wiki Activity
83,370 Commits 39 Branches 0 Tags 277 MiB
e7f702fc2d
Commit Graph

898 Commits

Author SHA1 Message Date
Craig Topper
e7f702fc2d Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 07:07:16 +00:00
Craig Topper
2123b18247 Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:55:37 +00:00
Craig Topper
081f931077 Fix build failures from r159106. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 06:08:31 +00:00
Craig Topper
66a69fa729 Remove intrinsic specific instructions for CVTPD2PS and replace with just patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159106 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:44:31 +00:00
Craig Topper
7f2ea14c68 Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-24 05:33:24 +00:00
Craig Topper
c82b9a51a2 Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 22:33:14 +00:00
Craig Topper
624a9c49d4 Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:52:45 +00:00
Craig Topper
6fc218e3a1 Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 20:15:42 +00:00
Craig Topper
fc76b8691e Use correct memory types for (V)CVTDQ2PD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159075 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 08:30:27 +00:00
Craig Topper
eea4a9b1e6 Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with intrinsic patterns. Mem forms omitted because the load size is only 64-bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-23 04:23:36 +00:00
Craig Topper
65d36f0367 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:30:23 +00:00
Craig Topper
af4166cd09 Add predicate check around some patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-20 07:01:11 +00:00
Kay Tiong Khoo
19e5015e5f *no need to pollute Intel syntax with bonus mnemonics; operand size is explicitly specified 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-16 17:19:49 +00:00
Craig Topper
3949b8382d Mark several instructions SSE2 instead of SSE3 as they should be. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-06 06:45:27 +00:00
Benjamin Kramer
c8e340da82 X86: Rename the CLMUL target feature to PCLMUL. 
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 14:34:17 +00:00
Craig Topper
0559a2f8ae Add intrinsic for pclmulqdq instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 04:37:40 +00:00
Benjamin Kramer
1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-29 19:05:25 +00:00
Craig Topper
189bce48c7 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156375 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 06:58:15 +00:00
Craig Topper
ef2b8bda02 Fix some issues in the f16c instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:00:15 +00:00
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:36:19 +00:00
Nadav Rotem
7bc9698f3a AVX: Add additional vbroadcast replacement sequences for integers. 
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 18:09:59 +00:00
Nadav Rotem
d1a79136e3 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions 
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-24 11:07:03 +00:00
Elena Demikhovsky
1da5867236 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-22 09:39:03 +00:00
Craig Topper
ffa6c40ecf Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154801 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 07:13:00 +00:00
Craig Topper
7e9f7fbc11 Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 06:26:15 +00:00
Craig Topper
8325c11d47 Merge vpermps/vpermd and vpermpd/vpermq SD nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-16 00:41:45 +00:00
Craig Topper
2cb1e9dc7d Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154778 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 22:43:31 +00:00
Nadav Rotem
f16af0a053 Fix PR12529. The Vxx family of instructions are only supported by AVX. 
Use non-vex instructions for SSE4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154770 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 19:36:44 +00:00
Elena Demikhovsky
73c504af9d Added VPERM optimization for AVX2 shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 11:18:59 +00:00
Craig Topper
bf596c9c61 Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-12 07:23:00 +00:00
Nadav Rotem
e611378a6e Reapply 154396 after fixing a test. 
Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:40:27 +00:00
Eric Christopher
a139051654 Temporarily revert this patch to see if it brings the buildbots back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 19:33:16 +00:00
Nadav Rotem
50e64cfe6e Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. 
blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 14:33:13 +00:00
Craig Topper
b45c969959 Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove patterns for selecting the intrinsic. Similar was already done for avx1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154272 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 22:32:29 +00:00
Craig Topper
f16ffb1259 Move vinsertf128 patterns near the instruction definitions. Add AddedComplexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-07 21:57:43 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 05:20:24 +00:00
Chad Rosier
1b1fdc0599 [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to 
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 21:43:40 +00:00
Chad Rosier
a3bfdf536e [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give 
precedence over the VINSERTF128 avx1 patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 19:45:07 +00:00
Chad Rosier
666da1611a Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 18:38:33 +00:00
Chad Rosier
36a273a76c [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 18:24:55 +00:00
Chad Rosier
33e528d44d [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:08:51 +00:00
Chad Rosier
38ca0d78a2 [avx] Add patterns for VINSERTF128rm. 
This results in things such as

	vmovaps	-96(%rbx), %xmm1
	vinsertf128	$1, %xmm1, %ymm0, %ymm0

to be combined to
         
	vinsertf128	$1, -96(%rbx), %ymm0, %ymm0

rdar://10643481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 00:45:30 +00:00
Kay Tiong Khoo
5a08cf4d34 *fix typo in comment; test of commit access 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 21:29:49 +00:00
Chad Rosier
abd6674166 Fix a regression from r147481. 
Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.

Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 02:00:48 +00:00
Preston Gurd
e879cbae7c This patch adds instruction latencies for the SSE instructions 
to the instruction scheduler for the Intel Atom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-27 23:35:03 +00:00
Pete Cooper
d18134f116 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-24 03:51:49 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
6e94e68b75 Remove the last of the old vector_shuffle patterns from X86 isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-17 07:02:34 +00:00
Craig Topper
233a64846e Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-14 08:14:53 +00:00