Commit Graph

108014 Commits

Author SHA1 Message Date
Adam Nemet
7cb345ea87 [X86] Improve comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 17:14:10 +00:00
Moritz Roth
9753aab704 ARM load/store optimizer: Don't materialize a new base register with
ADDS/SUBS unless it's safe to clobber the condition flags.

If the merged instructions are in a range where the CPSR is live,
e.g. between a CMP -> Bcc, we can't safely materialize a new base
register.

This problem is quite rare, I couldn't come up with a test case and I've
never actually seen this happen in the tests I'm running - there is a
potential trigger for this in LNT/oggenc (spills being inserted between
a CMP/Bcc), but at the moment this isn't being merged. I'll try to
reduce that into a small test case once I've committed my upcoming patch
to make merging less conservative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217881 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 16:25:07 +00:00
Benjamin Kramer
8be86aaf82 Spell out a move ctor. Even the 2013 vintage of MSVC cannot synthesize move ctors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217879 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 16:16:39 +00:00
Benjamin Kramer
a9478c4a96 Interpreter: Hack around a series of bugs in MSVC 2012 that copies around this
move-only struct.

I feel terrible now, but at least it's shielded away from proper compilers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217875 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 15:26:41 +00:00
Toma Tabacu
cdb6326c1f [mips] Improve the error messages given by MipsAsmParser.
Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 15:00:52 +00:00
Frederic Riss
baaa29f3a2 Make DWARFUnitSection final and change base class to non-virtual protected destructor.
As per dblaikie suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217871 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 12:58:01 +00:00
Toma Tabacu
e40de571ad [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td.
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5244



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 10:19:03 +00:00
Toma Tabacu
c6380f0b05 [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6.
Patch by Vasileios Kalintiris.

Differential Revision: http://reviews.llvm.org/D5242



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 09:26:09 +00:00
Joe Abbey
e9233b393a ARMAsmBackend uses a factory method to generate binary file format specific
objects.  There were a few FIXMEs in ARMAsmBackend.cpp suggesting the class
definitions should be in a separate file.  Starting with ARMAsmBackend, the
class definition has been put in a header file, and #includes reduced.  Each
sub-type of ARMAsmBackend is now in its own header file.

Derived types have been painted with a different color of bike-shed:

  s/DarwinARMAsmBackend/ARMAsmBackendDarwin/g
  s/ARMWinCOFFAsmBackend/ARMAsmBackendWinCOFF/g
  s/ELFARMAsmBackend/ARMAsmBackendELF/g

Finally, clang-format has been run across ARMAsmBackend.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 09:18:23 +00:00
Tilmann Scheller
359ae293f5 [InstCombine] Remove redundant test case.
Patch by Sonam Kumari!

Differential Revision: http://reviews.llvm.org/D5284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 08:50:10 +00:00
Elena Demikhovsky
0218e1e1da AVX-512: added cost for some AVX-512 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 07:57:37 +00:00
Justin Bogner
d41bba158c llvm-cov: Rename a variable and clean up its usage
Offset is a terrible name for an indentation / nesting level, and it
confuses me every time I look at this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 06:21:57 +00:00
Nick Kledzik
91737e133a tweak test case to help build bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 04:51:38 +00:00
Hal Finkel
8def8d9263 Fix BasicTTI::getCmpSelInstrCost to deal with illegal vector types
The default implementation of getCmpSelInstrCost, which provides the cost of
icmp/fcmp/select instructions, did not deal sensibly with illegal vector types
that were scalarized. We'd ask for the legalization cost of the vector type,
which would return something like (4, f64) given an input of <4 x double>, and
we'd then check the TLI status of the ISD opcode on that scalar type. This would
result in querying (ISD::VSELECT, f64), for example. Amusingly enough,
ISD::VSELECT on scalar types is marked as Legal by default (as with most other
operations), and most backends never change this because VSELECT is never
generated on scalars. However, seeing the resulting operation as Legal, we'd
neglect to add the scalarization cost before returning. The result is that we'd
grossly under-estimate the cost of cmps/selects on illegal vector types.

Now, if type legalization clearly results in scalarization, we skip the early
return and add the scalarization cost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217859 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 04:35:50 +00:00
David Majnemer
50c1eff629 yaml2obj: Support bigobj
Teach yaml2obj how to make a bigobj COFF file.  Like the rest of LLVM,
we automatically decide whether or not to use regular COFF or bigobj
COFF on the fly depending on how many sections the resulting object
would have.

This ends the task of adding bigobj support to LLVM.

N.B. This was tested by forcing yaml2obj to be used in bigobj mode
regardless of the number of sections.  While a dedicated test was
written, the smallest I could make it was 36 MB (!) of yaml and it still
took a significant amount of time to execute on a powerful machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 03:52:46 +00:00
Nick Kledzik
23ed1eab04 tweak test case to help solve why failing on one build bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217856 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 02:33:36 +00:00
Chandler Carruth
07b445aff7 [x86] Remove a FIXME that doesn't make any sense. Only the lanes feeding
the blend that is matched by this are "used" in any sense, and so any
build_vector or other nodes feeding these will already drop other lanes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217855 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 02:16:42 +00:00
Chandler Carruth
2f21b7ec5c [x86] Cleanup an unused variable by actually using it in the non-asserts
place where it was needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217854 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 02:14:51 +00:00
Nick Kledzik
367cf70f27 [llvm-objdump] for mach-o add -bind, -lazy-bind, and -weak-bind options
This finishes the ability of llvm-objdump to print out all information from
the LC_DYLD_INFO load command.

The -bind option prints out symbolic references that dyld must resolve 
immediately.

The -lazy-bind option prints out symbolc reference that are lazily resolved on 
first use.

The -weak-bind option prints out information about symbols which dyld must
try to coalesce across images.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217853 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 01:41:51 +00:00
Chandler Carruth
2e363ece75 [x86] Remove the last vestiges of the BLENDI-based ADDSUB pattern
matching. This design just fundamentally didn't work because ADDSUB is
available prior to any legal lowerings of BLENDI nodes. Instead, we have
a dedicated ADDSUB synthetic ISD node which is pattern matched trivially
into the instructions. These nodes are then recognized by both the
existing and a trivial new lowering combine in the backend. Removing
these patterns required adding 2 missing shuffle masks to the DAG
combine, without which tests would have failed. Added the masks and
a helpful assert as well to catch if anything ever goes wrong here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217851 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 00:39:08 +00:00
Juergen Ributzka
c9bc145e31 [FastISel][AArch64] Add vector support to argument lowering.
Lower the first 8 vector arguments too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217850 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 00:25:30 +00:00
Chandler Carruth
bad2c13aae [x86] As a follow-up to r217819, don't check for VSELECT legality now
that we don't use VSELECT and directly emit an addsub synthetic node.
Also remove a stale comment referencing VSELECT.

The test case is updated to use 'core2' which only has SSE3, not SSE4.1,
and it still passes. Previously it would not because we lacked
sufficient blend support to legalize the VSELECT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217849 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 00:24:42 +00:00
Chandler Carruth
cba9d1273a [x86] Add the beginnings of a proper DAG combine to match ADDSUBPS and
ADDSUBPD nodes out of blends of adds and subs.

This allows us to actually form these instructions with SSE3 rather than
only forming them when we had both SSE3 for the ADDSUB instructions and
SSE4.1 for the blend instructions. ;] Kind-of important.

I've adjusted the CPU requirements on one of the tests to demonstrate
this kicking in nicely for an SSE3 cpu configuration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-16 00:15:20 +00:00
Juergen Ributzka
c0f00e90d2 [FastISel][AArch64] Add missing test case for previous commit.
This adds the missing test case for the previous commit:
Allow handling of vectors during return lowering for little endian machines.

Sorry for the noise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 23:47:57 +00:00
Juergen Ributzka
488f228a4f [FastISel][AArch64] Allow handling of vectors during return lowering for little endian machines.
Allow handling of vectors during return lowering at least for little endian machines.
This was restricted in r208200 to fix it for big endian machines (according to
the comment), but it also disabled it for little endian too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217846 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 23:40:10 +00:00
Juergen Ributzka
d8629f313e [FastISel][AArch64] Update function and variable names to follow the coding standard. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217845 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 23:20:17 +00:00
David Blaikie
1bdc6c4519 DebugInfo: Add comment describing the need to disable address pool usage in skeleton units.
Post commit review from Eric Christopher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:41:25 +00:00
Juergen Ributzka
61c9638f41 [FastISel][AArch64] Make AArch64FastISel class final. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217840 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:33:11 +00:00
Juergen Ributzka
df445d7af2 [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.
Also lower sin/cos/pow to runtime lib calls.

This fixes rdar://problem/18343468.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217839 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:33:06 +00:00
Justin Bogner
16bd30fa48 llvm-cov: Make debug output more consistent
This changes the debug output of the llvm-cov tool to consistently
write to stderr, and moves the highlighting output closer to where
it's relevant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:23:29 +00:00
David Blaikie
ccaf6dd1d9 Fix indenting caused by clang-format+spuriously indented access specifier in r216925
Caught in post-commit review by Justin Bogner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:20:31 +00:00
Justin Bogner
47a75481e2 llvm-cov: Fix an issue with showing regions but not counts
In r217746, though it was supposed to be NFC, I broke llvm-cov's
handling of showing regions without showing counts. This should've
shown up in the existing tests, except they were checking debug output
that was displayed regardless of what was actually output. I've moved
the relevant debug output to a more appropriate place so that the
tests catch this kind of thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217835 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:12:28 +00:00
Rafael Espindola
d41a46e942 Add back tests for empty function in SPARC and PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217834 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:11:07 +00:00
Juergen Ributzka
323445f706 [FastISel][AArch64] Add lowering support for frem.
This lowers frem to a runtime libcall inside fast-isel.

The test case also checks the CallLoweringInfo bug that was exposed by this
change.

This fixes rdar://problem/18342783.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217833 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:07:49 +00:00
Juergen Ributzka
7d8b5f7777 [FastISel] Fix a bug in FastISel::CallLoweringInfo.
This fixes a bug in FastISel::CallLoweringInfo, where the number of
arguments was obtained from the argument vector before it had been
initialized.

Test case follows in another commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217832 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 22:07:44 +00:00
Sanjay Patel
ec6117cf1d Replace repeated null checks with an assert. NFC.
Without a vector to hold the created ops, these 
functions don't have any use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217831 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 21:52:51 +00:00
Nick Kledzik
9885a59108 [Support] add decodeSLEB128()
We already have routines to encode SLEB128 as well as encode/decode ULEB128.
This last function fills out the matrix.  I'll need this for some llvm-objdump
work I am doing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 21:51:49 +00:00
Juergen Ributzka
05cd1489c0 [FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. NFC.
Small refactor to tidy up the code a little.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217827 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 21:27:56 +00:00
Juergen Ributzka
4e10936b38 [FastISel][AArch64] Refactor code to use isTypeSupported. NFC.
Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217826 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 21:27:54 +00:00
Jingyue Wu
5e49dcf79a Remove dead code in SimplifyCFG
Summary: UsedByBranch is always true according to how BonusInst is defined.

Test Plan:
Passes check-all, and also verified 

if (BonusInst && !UsedByBranch) {
  ...
}

is never entered during check-all.

Reviewers: resistor, nadav, jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, eliben, meheff

Differential Revision: http://reviews.llvm.org/D5324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217824 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:48:13 +00:00
Juergen Ributzka
86bdc1efbe [FastISel][AArch64] Improve floating-point compare support.
Add support for the last two missing fcmp condition codes: UEQ and ONE.

This fixes rdar://problem/18341575.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217823 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:47:16 +00:00
Juergen Ributzka
1ee1e8bdc2 [FastISel] Move optimizeCmpPredicate to FastISel base class. NFC.
Make the optimizeCmpPredicate function available to all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:47:13 +00:00
Reed Kotler
34ad085eec Add mips32 r1 to the list of supported targets for Mips fast-isel
Summary:
Expand list of supported targets for Mips to include mips32 r1.
Previously it only include r2. More patches are coming where there is 
a difference but in the current patches as pushed upstream, r1 and r2
are equivalent.

Test Plan:
simplestorefp1.ll

add new build bots at mips to test this flavor at both -O0 and -O2

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5306

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:30:25 +00:00
David Majnemer
52d7b9c0aa Fix the build for MSVC, it doesn't support extended sizeof
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217820 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:28:38 +00:00
Chandler Carruth
fa6cf7e73c [x86] Start fixing our emission of ADDSUBPS and ADDSUBPD instructions by
introducing a synthetic X86 ISD node representing this generic
operation.

The relevant patterns for mapping these nodes into the concrete
instructions are also added, and a gnarly bit of C++ code in the
target-specific DAG combiner is replaced with simple code emitting this
primitive.

The next step is to generically combine blends of adds and subs into
this node so that we can drop the reliance on an SSE4.1 ISD node
(BLENDI) when matching an SSE3 feature (ADDSUB).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217819 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 20:09:47 +00:00
Sanjay Patel
6c7ec4aae9 Replace dead links to "Hacker's Delight" with general references. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217814 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:47:44 +00:00
David Majnemer
f1198da05c MC: Add support for BigObj
Teach WinCOFFObjectWriter how to write -mbig-obj style object files;
these object files allow for more sections inside an object file.

Our support for BigObj is notably different from binutils and cl: we
implicitly upgrade object files to BigObj instead of asking the user to
compile the same file *again* but with another flag.  This matches up
with how LLVM treats ELF variants.

This was tested by forcing LLVM to always emit BigObj files and running
the entire test suite.  A specific test has also been added.

I've lowered the maximum number of sections in a normal COFF file,
VS "14" CTP 3 supports no more than 65279 sections.  This is important
otherwise we might not switch to BigObj quickly enough, leaving us with
a COFF file that we couldn't link.

yaml2obj support is all that remains to implement.

Differential Revision: http://reviews.llvm.org/D5349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217812 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:42:42 +00:00
Benjamin Kramer
46738fc43e Add return that was lost somehow in my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217810 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:25:55 +00:00
Benjamin Kramer
9d38b2f76c Remove ancient hack that was emulating move semantics with reference counting.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217808 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:20:52 +00:00
NAKAMURA Takumi
85deed0525 llvm/test/CodeGen/X86/peephole-fold-movsd.ll: Relax an expression for win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 19:00:31 +00:00