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19669 Commits

Author SHA1 Message Date
Jim Grosbach
eeca7582fa Remove incorrect comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:45:50 +00:00
Owen Anderson
98c5ddabca Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:38:46 +00:00
Bruno Cardoso Lopes
6b5b79c7e8 Add a fixme note! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 23:04:24 +00:00
Jim Grosbach
c075d45364 Thumb2 assembly parsing and encoding for SHASX/SHSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:34:29 +00:00
Eli Friedman
74bf18ccea Minor cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:26:18 +00:00
Eli Friedman
7cc156647f Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:18:49 +00:00
Bruno Cardoso Lopes
b4e905d027 Add the remaining AVX versions of instructions to X86InstrInfo, this 
time for describing high latency ones and for recognizting loads
from the same base pointer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 22:15:52 +00:00
Bruno Cardoso Lopes
cd2857ee67 Factor out partial register update checks for some SSE instructions. 
Also add the AVX versions and add comments!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 21:42:23 +00:00
Jim Grosbach
e4e4a93e9e Thumb2 assembly parsing and encoding for SASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 21:01:23 +00:00
Jim Grosbach
191d33fd6d Thumb2 assembly parsing and encoding for RSB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 20:54:14 +00:00
Jim Grosbach
689b86ed2e Thumb2 assembly parsing and encoding for REV16/REVSH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 19:46:13 +00:00
Owen Anderson
ede042dc8d Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:36:29 +00:00
Bruno Cardoso Lopes
0c4b9ff077 Change all checks regarding the presence of any SSE level to always 
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:27:36 +00:00
Bruno Cardoso Lopes
41a9635292 Enable SSEDomainFix pass for AVX mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:27:32 +00:00
Jim Grosbach
1b69a128d6 Thumb2 assembly parsing and encoding for REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 18:13:30 +00:00
Jim Grosbach
b6e9a83349 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 16:16:50 +00:00
Jim Grosbach
57b21e437a Thumb2 push/pop mnemonic recognition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-15 15:55:04 +00:00
Eli Friedman
322ea080ad Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Issue spotted in -debug output. I can't think of any practical effects at the moment, but it might matter if we start doing more aggressive alias analysis in CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:42:45 +00:00
Jim Grosbach
0b69247b10 Thumb2 assembly parsing and encoding for PKH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:41 +00:00
Jim Grosbach
21a05e7017 ARMv7a has the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 23:16:34 +00:00
Jim Grosbach
e1d58a6556 ARM tighten up the register classes for the PKH instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:52:14 +00:00
Owen Anderson
8adf62034a Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 22:46:14 +00:00
Jim Grosbach
d32872f9ca Thumb2 assembly parsing and encoding for MVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:24:41 +00:00
Owen Anderson
34626acf7f Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:06:21 +00:00
Jim Grosbach
64944f48a1 Thumb2 assembly parsing and encoding for MUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 21:00:40 +00:00
Jim Grosbach
bf841cf336 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 20:03:46 +00:00
Jim Grosbach
c2d3164ab4 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 19:12:11 +00:00
Jim Grosbach
d0588e2a2e ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 18:08:35 +00:00
Akira Hatanaka
0b7b6a0856 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 17:22:51 +00:00
Craig Topper
a08e255e1e Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 06:41:26 +00:00
Craig Topper
3bb43a829e Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139690 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 05:55:28 +00:00
Bruno Cardoso Lopes
c4cc40c001 One more patch towards JIT support for Mips. 
- Add TSFlags for the instruction formats. The idea here is to use
  as much encoding as possible from getBinaryCodeForInstr, and having
  TSFLags formats for that would make it easier to encode most part
  of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding

Commit msg added by my own but the patch is from Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 03:00:41 +00:00
Bruno Cardoso Lopes
484ddf54c9 Teach the foldable tables about 128-bit AVX instructions and make the 
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.

Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.

256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 02:36:58 +00:00
Bruno Cardoso Lopes
5ca0d14915 Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139686 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 02:36:14 +00:00
Jim Grosbach
d300b94e51 Remove unnecessary scope resolution operator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 22:56:44 +00:00
Owen Anderson
7782a58b87 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:46:26 +00:00
Jim Grosbach
d7a2b3bea8 There's only 16 regs legal in a register list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:35:57 +00:00
Jim Grosbach
b04546ff5b Tidy up a few 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:30:37 +00:00
Jim Grosbach
8f310d9786 Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:27:44 +00:00
Akira Hatanaka
a4b97f327d Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 20:13:58 +00:00
Nadav Rotem
dfb5935c76 swap vselect operand order - pr10907 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:56:38 +00:00
Bruno Cardoso Lopes
df24e1fb08 Add versions 256-bit versions of alignedstore and alignedload, to be 
more strict about the alignment checking. This was found by inspection
and I don't have any testcases so far, although the llvm testsuite runs
without any problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:33:03 +00:00
Bruno Cardoso Lopes
809f17fbb1 Revert the remaining part of r139528. According to PR10907 the bug seems 
to be in the VSELECT operands order, so I'll leave the fix for Nadav.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139624 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:33:00 +00:00
Nadav Rotem
aec5861bb6 Add vselect target support for targets that do not support blend but do support 
xor/and/or (For example SSE2).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 19:17:42 +00:00
Akira Hatanaka
48ae99fac4 Support for PSP is gone too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 18:55:33 +00:00
Owen Anderson
b6b7f515e2 Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:59:19 +00:00
Akira Hatanaka
2152307933 It is not necessary to search for mipsallegrex in target triple string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:35:28 +00:00
Owen Anderson
12c7e90d36 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 17:34:32 +00:00
Craig Topper
4bbeb18f76 Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139591 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 07:37:44 +00:00
Craig Topper
58bbb81764 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 06:54:58 +00:00