Commit Graph

3978 Commits

Author SHA1 Message Date
NAKAMURA Takumi
f5677777ca lit: Pass %INCLUDE% to tests on Win32. clang may expect existence of %INCLUDE% in vcvarsall.bat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 00:02:06 +00:00
Benjamin Kramer
3c39cd8491 DFAPacketizerEmitter: Prune includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12 21:32:58 +00:00
Craig Topper
c5eaae4e9b Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11 07:57:25 +00:00
Craig Topper
39bdc5526f Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to reduce size of static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11 01:57:56 +00:00
Kevin Enderby
faf72ffda3 Fix the x86 disassembler to at least print the lock prefix if it is the first
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 17:52:49 +00:00
NAKAMURA Takumi
89d8139d37 TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.
~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152407 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 14:52:44 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 08:22:45 +00:00
Craig Topper
88d2fa438a Re-commit r152202 hopefully fixing the MSVC linker error.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 06:55:27 +00:00
Chad Rosier
3c777947f4 Revert r152202 as it's causing internal buildbot failures.
Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect 
all 16-bit string table offsets. Also make sure the string to offset table 
string is not larger than 65536 characters since larger string literals aren't 
portable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 17:06:40 +00:00
Craig Topper
d3c9d9447e Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152202 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:17:23 +00:00
Jim Grosbach
4d0983a4d7 ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:10:38 +00:00
Jim Grosbach
c0fc450f07 ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 22:01:44 +00:00
Owen Anderson
40530ad3a8 Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 21:48:32 +00:00
Craig Topper
f0c094b115 Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 06:04:39 +00:00
Craig Topper
904a01820c Add asserts to ensure that values will fit into the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 04:39:52 +00:00
Jim Grosbach
7cc0426489 Nuke a bit of dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 23:09:51 +00:00
Jim Grosbach
c3384c93c0 ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 21:43:40 +00:00
Jim Grosbach
28f08c93e7 ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:33:30 +00:00
Craig Topper
52b89dd303 Shrink and reorder fields in MCRegisterClass to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 08:33:33 +00:00
Craig Topper
9ebfbf8b9f Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 05:37:41 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Craig Topper
b6632ba380 Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:16:38 +00:00
Craig Topper
015f228861 Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 03:33:22 +00:00
Craig Topper
991271d9c4 Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 02:16:41 +00:00
Benjamin Kramer
b08bb34a6f Perform the string table optimization for OperandMatchEntries too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151986 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03 20:44:43 +00:00
Benjamin Kramer
a4c5ecfb1b Shrink the asm matcher tables.
- Shrink the opcode field to 16 bits.
- Shrink the AsmVariantID field to 8 bits.
- Store the mnemonic string in a string table, store a 16 bit index.
- Store a pascal-style length byte in the string instead of a null terminator,
  so we can avoid calling strlen on every entry we visit during mnemonic search.

Shrinks X86AsmParser.o from 434k to 201k on x86_64 and eliminates relocs from the table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03 19:13:26 +00:00
Benjamin Kramer
02ee75393f StringToOffsetTable: Allow uniquing the first element, add an option to skip appending a terminating null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03 19:13:20 +00:00
Duncan Sands
61318736ee Honour --config-prefix also for lit.local.cfg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151977 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03 13:30:56 +00:00
Benjamin Kramer
4b1212b4bf Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 18:16:35 +00:00
Jim Grosbach
b3acdcc00c Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.
Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 17:30:39 +00:00
Jim Grosbach
194f3fa9ea Revert "Emit the SubRegTable with the smallest possible integer type."
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 17:30:35 +00:00
Benjamin Kramer
ccc8d3ba06 Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.

Shrinks ARMBaseRegisterInfo.o by ~100k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 13:37:55 +00:00
Benjamin Kramer
36a2138cce Emit the "is an intrinsic overloaded" table as a bitfield.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 02:16:57 +00:00
Benjamin Kramer
b519a0fe0e Emit the intrinsic modref info as a lookup table instead of a huge switch.
Shrinks BasicAliasAnalysis.o from 106k to 56k on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 01:18:32 +00:00
Benjamin Kramer
6c449ebbe6 Implement getSubRegIndex as a linear search on the SubRegTable instead of using a big switch.
- The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts.
- This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 23:46:50 +00:00
Jim Grosbach
9c826d2d3c Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 22:07:56 +00:00
Benjamin Kramer
b9ace0215d Emit the SubRegTable with the smallest possible integer type.
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:57:08 +00:00
Jim Grosbach
eea87153d1 Tidy up. Spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:46:32 +00:00
Jim Grosbach
5d9651df89 Move the subregister indicies enum into the REGINFO_ENUM section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 21:43:16 +00:00
Jim Grosbach
95b38aea95 Switch TargetRegisterInfo::getSubReg() to use a lookup table.
Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 20:31:17 +00:00
Craig Topper
1f59523521 Convert generated intrinsic attributes to use an array lookup as Chris suggested in PR11951.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 06:32:00 +00:00
Craig Topper
a1c5b8e1e6 Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 02:31:09 +00:00
Craig Topper
930a1ebd92 X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
Craig Topper
9d91c5d31c Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that were added in r151038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 08:42:06 +00:00
Bill Wendling
13b151c111 Remove bad comma from .el file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 19:38:03 +00:00
David Greene
cebb4ee93a Add Foreach Loop
Add some data structures to represent for loops.  These will be
referenced during object processing to do any needed iteration and
instantiation.

Add foreach keyword support to the lexer.

Add a mode to indicate that we're parsing a foreach loop.  This allows
the value parser to early-out when processing the foreach value list.

Add a routine to parse foreach iteration declarations.  This is
separate from ParseDeclaration because the type of the named value
(the iterator) doesn't match the type of the initializer value (the
value list).  It also needs to add two values to the foreach record:
the iterator and the value list.

Add parsing support for foreach.

Add the code to process foreach loops and create defs based
on iterator values.

Allow foreach loops to be matched at the top level.

When parsing an IDValue check if it is a foreach loop iterator for one
of the active loops.  If so, return a VarInit for it.

Add Emacs keyword support for foreach.

Add VIM keyword support for foreach.

Add tests to check foreach operation.

Add TableGen documentation for foreach.

Support foreach with multiple objects.

Support non-braced foreach body with one object.

Do not require types for the foreach declaration.  Assume the iterator
type from the iteration list element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 16:09:41 +00:00
Craig Topper
c528e462a1 Declare register classes as const. Fix a couple pointers to register classes that weren't already const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 07:28:11 +00:00
Craig Topper
44d23825d6 Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
Craig Topper
7d9b20792b Reorder some members in MCRegisterClass to remove padding on 64-bit builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 07:36:39 +00:00
Craig Topper
f3e3783012 In generated RegisterInfo files, replace a pointer to the end of an array with just the size of the array to avoid relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21 06:54:41 +00:00