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8591 Commits

Author SHA1 Message Date
Chad Rosier
f58ae5dfc1 [ms-inline asm] Make the operand size directives case insensitive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163729 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 18:24:26 +00:00
Roman Divacky
ee3392b1a9 Add support for AMD Geode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163710 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 14:36:02 +00:00
Craig Topper
7c02284774 Indentation fixes. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163682 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-12 06:20:41 +00:00
Manman Ren
b720be6a50 Release build: guard dump functions with 
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 22:23:19 +00:00
Chad Rosier
66b64bec60 StringSwitchify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163649 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 21:10:25 +00:00
Chad Rosier
aa645f78a2 Simplify logic. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163648 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 20:57:04 +00:00
Craig Topper
55b2405484 Make a bunch of lowering helper functions static instead of member functions. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 06:15:32 +00:00
Craig Topper
9e6dc8b9e7 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-11 04:19:21 +00:00
Chad Rosier
35c688932a Update function names to conform to guidelines. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163561 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:50:57 +00:00
Chad Rosier
1dc2591e9e Revert r163556. Missed updates to tablegen files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163557 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:30:35 +00:00
Chad Rosier
16c5584548 Update function names to conform to guidelines. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 22:23:45 +00:00
Dmitri Gribenko
2de0572cae Remove redundant semicolons which are null statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:26:47 +00:00
Chad Rosier
3b132fab0b [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() function 
and update the printOperand() function accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163544 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 21:10:49 +00:00
Chad Rosier
3c4ecd7dab [ms-inline asm] Add support for .att_syntax directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 20:54:39 +00:00
Michael Liao
b8150d8523 Enhance PR11334 fix to support extload from v2f32/v4f32 
- Fix an remaining issue of PR11674 as well



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 18:33:51 +00:00
Michael Liao
7fdc66bf73 Add boolean simplification support from CMOV 
- If a boolean value is generated from CMOV and tested as boolean value,
  simplify the use of test result by referencing the original condition.
  RDRAND intrinisc is one of such cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 16:36:16 +00:00
Elena Demikhovsky
8100d244ff The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer. 
I've added the "zeroinitializer" case in this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 12:13:11 +00:00
Nick Lewycky
74eab5ab9e Add missing space before {. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163484 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-09 23:40:55 +00:00
Craig Topper
12fb5c667f Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-08 17:42:27 +00:00
Craig Topper
cacd9d6f79 Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163463 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-08 07:46:05 +00:00
Craig Topper
4362067d7c Add support for lowering FABS of vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163461 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-08 07:31:51 +00:00
Craig Topper
a1fb1d2ed7 Set operation action for FFLOOR to Expand for all vector types for X86. Set FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-08 04:58:43 +00:00
Benjamin Kramer
8e70b5506e PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for registers. 
gas accepts this and it seems to be common enough to be worth supporting. This
doesn't affect the parsing of reg operands outside of .cfi directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-07 14:51:35 +00:00
Manman Ren
77e300e8f0 Release build: guard dump functions with "ifndef NDEBUG" 
No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 19:06:06 +00:00
Elena Demikhovsky
4178946afb AVX2 optimization. 
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 12:42:01 +00:00
Michael Liao
7859f438e1 Remove duplicated helper function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 07:11:22 +00:00
Craig Topper
b8d9da13fa Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 06:09:01 +00:00
Craig Topper
07149fe715 Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 05:15:01 +00:00
Roman Divacky
5932429765 Stop casting away const qualifier needlessly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 22:26:57 +00:00
Roman Divacky
b438615abd Use const properly so that we dont remove const qualifier from region and MII 
by casting. Found with gcc48.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163247 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 21:17:34 +00:00
Craig Topper
4e4e6c0d73 Remove some of the patterns added in r163196. Increasing the complexity on insert_subvector into undef accomplishes the same thing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163198 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 07:26:35 +00:00
Craig Topper
c17177f893 Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163196 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 06:58:39 +00:00
Craig Topper
f6dc792df1 Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163192 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 05:48:09 +00:00
Chad Rosier
5d637d7e93 Fix function name per coding standard. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-05 01:15:43 +00:00
Preston Gurd
2e2efd9600 Generic Bypass Slow Div 
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder,  or both.

Patch by Tyler Nowicki!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-04 18:22:17 +00:00
Elena Demikhovsky
3251020738 This patch optimizes shuffle instruction - generates 2 instructions instead of 4. 
Since this specific shuffle is widely used in many workloads we have ~10% performance on them.

shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>

vmovaps (%rdx), %ymm0
vshufps $8, %ymm0, %ymm0, %ymm0
vmovaps (%rcx), %ymm1
vshufps $8, %ymm0, %ymm1, %ymm1
vunpcklps       %ymm0, %ymm1, %ymm0

vmovaps (%rcx), %ymm0
vmovsldup       (%rdx), %ymm1
vblendps        $85, %ymm0, %ymm1, %ymm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-04 12:49:02 +00:00
Chad Rosier
2cc97def74 [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add 
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-03 20:31:23 +00:00
Chad Rosier
038f3e3127 [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the 
MCTargetAsmParser class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-03 18:47:45 +00:00
Chad Rosier
c4d2560a20 Removed unused argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-03 03:16:09 +00:00
Chris Lattner
8a04e51d86 some peepholes that should match horizontal add/sub operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-03 02:58:21 +00:00
Chad Rosier
3a86e13962 [ms-inline asm] Expose the Kind and Opcode variables from the 
MatchInstructionImpl() function.

These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-03 02:06:46 +00:00
Craig Topper
8365e9bcc2 Typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-01 06:33:50 +00:00
Manman Ren
2b7a2e8833 SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure its 
output chain is correctly setup.

As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.

rdar://11457792


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 23:16:57 +00:00
Craig Topper
dfb1e4babd Mark FMA4 instructions as commutable and add them to the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 23:10:34 +00:00
Craig Topper
bbdbb0550b Add selection of RegOp2MemOpTable3 to canFoldMemoryOperand 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163029 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 22:12:16 +00:00
Michael Liao
265bcb1e5b Fix PR12359 
- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as
  well as PSHUFB will zero elements with negative indices.

  Patch by Sriram Murali <sriram.murali@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163018 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 20:12:31 +00:00
Chad Rosier
5d04a560a8 The ConvertToMCInst() function can't fail, so remove the now dead Match_ConversionFail enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163002 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 16:41:07 +00:00
Craig Topper
cb0848696d Mark FMA3 instructions as commutable so that the operands to the multiply part can be commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 16:31:13 +00:00
Craig Topper
bf4043768c Add support for converting llvm.fma to fma4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 15:40:30 +00:00
Michael Liao
5d60c67318 Clean up AddedComplexity further after adding UseSSEx 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162973 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 03:01:35 +00:00