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f6f77e90a1
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2689 Commits

Author SHA1 Message Date
Sebastian Pop
f6f77e90a1 add missing point at the end of sentences 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-06 17:34:11 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-02 23:34:39 +00:00
Dylan Noblesmith
85bef06a2e TableGen: fix CMake build s'more 
Oops, missed another missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:53:39 +00:00
Anshuman Dasgupta
dc81e5da27 Add a deterministic finite automaton based packetizer for VLIW architectures 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 21:10:21 +00:00
Jim Grosbach
4a2242cea0 Replace an assert() with an actual diagnostic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 23:16:25 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 18:21:25 +00:00
Jim Grosbach
d4578a4f8d llvm_unreachable() is not for user diagnostics.... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:15:55 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:09:44 +00:00
Craig Topper
787a88ff18 Remove some unnecessary filtering checks from X86 disassembler table build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 05:48:20 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 01:02:57 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:46:57 +00:00
Jim Grosbach
2a8cd57566 Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:05:12 +00:00
Daniel Dunbar
8396893fa5 LLVMBuild: Alphabetize required_libraries lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:59:23 +00:00
Owen Anderson
1ad1246bbc Remove this from the CMake build since I erased the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:07:22 +00:00
Owen Anderson
a25e292d5f Remove the old-style ARM disassembler, which is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:56:06 +00:00
Craig Topper
c8eb880a7f More AVX2 instructions and their intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 23:04:08 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Chandler Carruth
1bfc9f8ff2 The TableGen parts of the CMake build are seriously broken. This fixes 
one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.

Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 05:03:06 +00:00
Jim Grosbach
48c1f84b10 Allow InstAlias's to use immediate matcher patterns that xform the value. 
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:32:53 +00:00
Jim Grosbach
be5d6bcfc6 Allow register classes to match a containing class in InstAliases. 
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:43:40 +00:00
Jim Grosbach
e39102819e Delete dead code. Nothing ever instantiates this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 21:59:17 +00:00
Craig Topper
75485d6746 Add X86 RORX instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 07:34:00 +00:00
Benjamin Kramer
1a2f9886a2 Move various generated tables into read-only memory, fixing up const correctness along the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 16:50:00 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:22:00 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:09:09 +00:00
Jim Grosbach
0e387b2877 ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:03 +00:00
Owen Anderson
684dfcf724 Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 16:56:47 +00:00
Benjamin Kramer
af482cf301 Pick low-hanging MatchEntry shrinkage fruit. 
Shaves 200k off Release-Asserts clang binaries on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 16:18:09 +00:00
Craig Topper
ee62e4f6d1 Add X86 PEXTR and PDEP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 16:50:08 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:05:40 +00:00
Craig Topper
17730847d5 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 03:51:13 +00:00
Craig Topper
566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-15 20:46:47 +00:00
Craig Topper
54a11176f6 Add X86 ANDN instruction. Including instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 07:06:56 +00:00
Jakob Stoklund Olesen
ccbe603869 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 01:00:49 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Eli Friedman
830378f662 Remove extra semicolon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 19:53:40 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Jakob Stoklund Olesen
819a2abc72 Emit full ED initializers even for pseudo-instructions. 
This should unbreak the picky buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 20:15:49 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:30:16 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:35:38 +00:00
Peter Collingbourne
6d1409dcc5 Remove the Clang tblgen backends from LLVM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 13:21:42 +00:00