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919 Commits

Author SHA1 Message Date
Tom Stellard
cd0b8d6cbf R600/SI: Emit an error when attempting to spill VGPRs v4 
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:41 +00:00
Tom Stellard
48d11b0228 R600/SI: Fix a crash when spilling SGPRs 
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:38 +00:00
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:54:59 +00:00
Tom Stellard
f586a260ca SelectionDAG: Expand SELECT_CC to SELECT + SETCC 
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 16:01:22 +00:00
Matt Arsenault
405ed284b7 R600/SI: Rename VOP3 helper class to be more general 
It has other uses besides shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210478 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 17:00:46 +00:00
Matt Arsenault
1968da36ed R600/SI: Keep 64-bit not on SALU 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 16:36:31 +00:00
Matt Arsenault
cf7a113d2f R600: Fix selection failure for vector bswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-09 16:20:25 +00:00
Matt Arsenault
798a829eca R600/SI: Match rsq instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210226 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-05 00:15:55 +00:00
Matt Arsenault
6db82d3819 Use nullptr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210222 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-05 00:01:12 +00:00
Matt Arsenault
1b68686365 Fix typos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210135 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-03 23:06:13 +00:00
Matt Arsenault
3871a03035 R600: Set all float vector expands in the same place 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-01 07:38:21 +00:00
Matt Arsenault
606b80c8c4 R600/SI: Remove redundant patterns 
These patterns are already handled in the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209979 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-31 19:25:17 +00:00
Matt Arsenault
da5824d073 R600/SI: Fix [s|u]int_to_fp for i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209971 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-31 06:47:42 +00:00
Matt Arsenault
bf933548ba R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209787 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-29 01:18:01 +00:00
Matt Arsenault
fed4bab148 R600: Add definition for flat address space ID. 
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209463 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:27:07 +00:00
Matt Arsenault
3c698f35e0 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209462 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:12 +00:00
Matt Arsenault
e3ed404672 R600: Add dag combine for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209461 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:07 +00:00
Matt Arsenault
7e12b82625 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209460 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:03 +00:00
Matt Arsenault
9859540b06 R600: Implement computeMaskedBitsForTargetNode for BFE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209459 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:09:00 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:15 +00:00
Matt Arsenault
351c658fc2 R600/SI: Move instruction pattern to instruction definition 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209454 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 17:45:20 +00:00
Matt Arsenault
bce7d05ba9 R600/SI: Match fp_to_uint / uint_to_fp for f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209388 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 03:20:30 +00:00
Matt Arsenault
afd1747bbc R600: Add comment describing problems with LowerConstantInitializer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209333 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-21 22:59:17 +00:00
Matt Arsenault
bd124c85ef R600: Partially fix constant initializers for structs and vectors. 
This should extend the current workaround to work with structs
that only contain legal, scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209331 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-21 22:42:42 +00:00
Matt Arsenault
49323774b4 Use cast<> instead of unchecked dyn_cast 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209310 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-21 18:03:59 +00:00
Matt Arsenault
f5d9170e67 Remove unused method declaration 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209174 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-19 22:55:35 +00:00
Aaron Ballman
50d09f1212 Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-19 14:29:04 +00:00
Tom Stellard
17200e3bb3 R600/SI: Refactor the VOP3_32 tablegen class 
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:47 +00:00
Tom Stellard
9d99d7a185 R600/SI: Add a PredicateControl class for managing TableGen predicates 
This was inspired by the PredicateControl class in the MIPS backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209027 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:45 +00:00
Tom Stellard
9b24e0c6f2 R600/SI: Move tablegen patterns away from instruction defs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209026 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:44 +00:00
Tom Stellard
1c073c3954 R600/SI: Remove unused instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209025 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:43 +00:00
Tom Stellard
3bd63cd655 R600/SI: Promote f32 SELECT to i32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209024 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:41 +00:00
Tom Stellard
03b96200c6 R600/SI: Remove duplicate pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209023 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-16 20:56:37 +00:00
Matt Arsenault
a8f7afaeb4 Use range for 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208922 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-15 21:44:05 +00:00
Tom Stellard
29d4ed329e R600/SI: Stop using VSrc_* as the default register class for types. 
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208888 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-15 14:41:57 +00:00
Tom Stellard
704fe35d88 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies 
This prevents a future commit from regressing the load-i1.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-15 14:41:55 +00:00
Tom Stellard
c1de569ce8 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-15 14:41:54 +00:00
Tom Stellard
bfffad69b2 R600/SI: Use VALU instructions for i1 ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-15 14:41:50 +00:00
Jay Foad
6b543713a2 Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-14 21:14:37 +00:00
Matt Arsenault
dda22295e4 R600/SI: Try to fix BFE operands when moving to VALU 
This was broken by r208479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208740 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-13 23:45:50 +00:00
Matt Arsenault
8655b1266f Use cast<> for unchecked use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 20:42:57 +00:00
Matt Arsenault
b36e348af3 Use cast<> for unchecked use 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:26:38 +00:00
Matt Arsenault
76aa42c199 Use range for 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 19:23:21 +00:00
Matt Arsenault
5049ca67c2 R600: Add mul24 intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-12 17:49:57 +00:00