stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
truncating an SDValue (depending on whether the target
type is bigger or smaller than the value's type); or zero
extending or truncating it. Use it in a few places (this
seems to be a popular operation, but I only modified cases
of it in SelectionDAGBuild). In particular, the eh_selector
lowering was doing this wrong due to a repeated rather than
inverted test, fixed with this change.
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is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
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While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83684 91177308-0d34-0410-b5e6-96231b3b80d8
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
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a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
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to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
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basic blocks that are so long that their size overflows a short.
Also assert that overflow does not happen in the future, as requested by Evan.
This fixes PR4401.
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- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
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naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
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this adjustment does not change the direction or the signs of the object
offsets, and the details of the offset calculations can be target-specific.
Also mention that for most targets this value is only used to generate debug
info.
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of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.
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two different places for printing MachineMemOperands.
Drop the virtual from Value::dump and instead give Value a
protected virtual hook that can be overridden by subclasses
to implement custom printing. This lets printing be more
consistent, and simplifies printing of PseudoSourceValue
values.
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the base pointer, without the offset. This matches MemSDNode's
new alignment behavior, and holds more interesting information.
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This can be seen on CodeGen/Generic/2006-09-06-SwitchLowering.ll. But it's not known to cause any real regression (but I have added an assertion for it now).
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one implementation into its one caller. This eliminates a totally
awesome and gratuitous hack where we casted a Function* to
GlobalVariable*.
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DAG Combiner to disambiguate chains for loads and stores of types which are
broken up by the Legalizer into smaller pieces.
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The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals.
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now that printBasicBlockLabel is only used for starting
a MBB. This allows elimination of a bunch of arguments.
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Move GetMBBSymbol up to AsmPrinter and make printBasicBlockLabel use it so that
we only have one place that decides what to name bb labels. Hopefully various
clients of printBasicBlockLabel can start using GetMBBSymbol instead.
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the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
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linear scan reg alloc. This fixes a problem I ran into where extracting
a function from a larger file caused the generated code to change (masking
the problem I was trying to debug) because the allocator behaved differently.
This changes the results for two X86 regression checks. stack-color-with-reg
is improved, with one less instruction, but pr3495 is worse, with one more
copy. As far as I can tell, these tests were just getting lucky or unlucky,
so I've changed the expected results.
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a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
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A include/llvm/ADT/iterator.cmake
U autoconf/configure.ac
--- Reverse-merging r80161 into '.':
U cmake/config-ix.cmake
--- Reverse-merging r80171 into '.':
U Makefile
--- Reverse-merging r80173 into '.':
U configure
U include/llvm/Config/config.h.in
--- Reverse-merging r80180 into '.':
A include/llvm/ADT/iterator.h.in
Despite common miscomceptions, iterator.h is alive and well. It broke the build
bots for several hours. And yet no one bothered to look at them.
Gabor and Doug, please review your changes and make sure that they actually
build before resubmitting them.
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This time there is no additional include of llvm/Config/config.h
at all. Instead I use a hard-coded preprecessor symbol:
LLVM_COMPACTIFY_SENTINELS
(should this work on the self-hosting buildbot, then
cleanups come next)
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This change speeds up llvm-gcc by more then 6% at "-O0 -g" (measured by compiling InstructionCombining.cpp!)
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U include/llvm/BasicBlock.h
U include/llvm/ADT/ilist_node.h
U include/llvm/ADT/ilist.h
U include/llvm/CodeGen/SelectionDAG.h
U include/llvm/CodeGen/MachineFunction.h
U include/llvm/CodeGen/MachineBasicBlock.h
U include/llvm/Function.h
Revert r79938. It was causing self-hosting build failures.
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reduce the size of relevant "ghostly" sentinels
by a pointer.
This attempt now makes the compactification dependent
on the configure variable LLVM_COMPACT_SENTINELS
and should not cause any bootstrap failures for
llvm-gcc any more.
Please note that this is not yet the final version,
and (as settled with Chris) I shall take out the
autofoo/cmake portions in the next days.
This will also lose the assertability on sentinel
dereferencing and operator++, but that seems
an acceptable price to pay for the simplified
build logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79938 91177308-0d34-0410-b5e6-96231b3b80d8
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
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bytes. libgcc doesn't seem to mind, but if you pass this DWARF to GDB, it
doesn't like it.
Also make the JIT memory manager to initialize it's memory to garbage in debug
mode, so that it's easier to find bugs like these in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79674 91177308-0d34-0410-b5e6-96231b3b80d8
gcc-4.4 was optimizing away comparisons against SimpleValueType when
it was compared to a value larger than the largest value in the enum.
This patch works around it by adding one extra item to the enum so
that these tests will now be valid.
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- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
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MCAsmStreamer. Based on this, eliminate the current section from AsmPrinter.
While I'm at it, clean up the last of the horrible "switch to null section" stuff
and add an assert. This change is in preparation for completely eliminating
asmprinter::switchtosection.
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more properly belong. This allows removing the front-end conditionalized
SJLJ code, and cleans up the generated IR considerably. All of the
infrastructure code (calling _Unwind_SjLj_Register/Unregister, etc) is
added by the SjLjEHPrepare pass.
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