Commit Graph

91833 Commits

Author SHA1 Message Date
Ulrich Weigand
fcdfd5a7ff [PowerPC] Avoid using '$' in generated assembler code
PowerPC assemblers are supposed to support a stand-alone '$' symbol
as an alternative of '.' to refer to the current PC.  This does not
work in the LLVM assembler parser yet.

To avoid bootstrap failures when using the LLVM assembler as system
assembler, this patch modifies the assembler source code generated
by LLVM to avoid using '$' (and simply use '.' instead).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:53:04 +00:00
Ulrich Weigand
a7e5e6b959 [PowerPC] Parse platform-specifc variant kinds in AsmParser
This patch adds support for PowerPC platform-specific variant
kinds in MCSymbolRefExpr::getVariantKindForName, and also
adds a test case to verify they are translated to the appropriate
fixup type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:52:35 +00:00
Ulrich Weigand
8e4ba8f7b1 [PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser.  These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.

The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics.  Again, those that are not yet
supported as marked as FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:51:09 +00:00
Ulrich Weigand
16adfdb2e6 [PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser.  It adds support specifically for those
extended mnemonics that LLVM will itself generate.

The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:50:27 +00:00
Ulrich Weigand
5e220753ff [PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux.  The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated.  (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings.  The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector. 
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features.  When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:49:39 +00:00
Shuxin Yang
968d689ec3 Decompose GVN::processNonLocalLoad() (about 400 LOC) into smaller helper functions. No function change.
This function consists of following steps:
   1. Collect dependent memory accesses.
   2. Analyze availability.
   3. Perform fully redundancy elimination, or 
   4. Perform PRE, depending on the availability

 Step 2, 3 and 4 are now moved to three helper routines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181047 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:17:26 +00:00
Akira Hatanaka
a2b2200ff8 [mips] Split the DSP control register and define one register for each field of
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 18:37:49 +00:00
Nadav Rotem
4bcd5f888f LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming values.
By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements.

We can now vectorize this loop:

int foo(int *A, int *B, int n) {
  for (int i=0; i < n; i++) {
    int x = 9;
    if (A[i] > B[i]) {
      if (A[i] > 19) {
        x = 3;
      } else if (B[i] < 4 ) {
        x = 4;
      } else {
        x = 5;
      }
    }
    A[i] = x;
  }
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:42:55 +00:00
Tom Stellard
19301d5d12 R600: Expand vector or, shl, srl, and xor nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:31 +00:00
Tom Stellard
8b1c60c151 R600: BFI_INT is a vector-only instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:24 +00:00
Tom Stellard
83f0a5a5e8 R600: Add pattern for SHA-256 Ma function
This can be optimized using the BFI_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:20 +00:00
Tom Stellard
218b20a81e R600: Clean up comments in Processors.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 17:21:14 +00:00
Benjamin Kramer
5212b4eb71 Autoconf: Compile cxxabi.h in C++ mode.
Should fix PR15877.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 15:55:06 +00:00
Tobias Grosser
333403abbd RegionInfo: Do not crash if unreachable block is found
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 15:48:34 +00:00
Benjamin Kramer
e050e59a47 CMake: cxxabi.h is only available to C++ compilers, use the right check macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 14:48:29 +00:00
Richard Sandiford
d07d29213b Remove comment that no target supports 128-bit IEEE floats
The soon-to-be-committed SystemZ port uses 128-bit IEEE floats.
MIPS64 GNU/Linux does too (albeit with unusual NaNs).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 14:32:27 +00:00
Richard Sandiford
6fc2ad62e2 [SystemZ] Add MCJIT support
Another step towards reinstating the SystemZ backend.  I'll commit
the configure changes separately (TARGET_HAS_JIT etc.), then commit
a patch to enable the MCJIT tests on SystemZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 14:15:35 +00:00
Ulrich Weigand
3ea50a69d7 [SystemZ] Support System Z as host architecture
The llvm::sys::AddSignalHandler function (as well as related routines) in
lib/Support/Unix/Signals.inc currently registers a signal handler routine
via "sigaction".  When this handler is called due to a SIGSEGV, SIGILL or
similar signal, it will show a stack backtrace, deactivate the handler,
and then simply return to the operating system.  The intent is that the
OS will now retry execution at the same location as before, which ought
to again trigger the same error condition and cause the same signal to be
delivered again.  Since the hander is now deactivated, the OS will take
its default action (usually, terminate the program and possibly create
a core dump).

However, this method doesn't work reliably on System Z:  With certain
signals (namely SIGILL, SIGFPE, and SIGTRAP), the program counter stored
by the kernel on the signal stack frame (which is the location where
execution will resume) is not the instruction that triggered the fault,
but then instruction *after it*.  When the LLVM signal handler simply
returns to the kernel, execution will then resume at *that* address,
which will not trigger the problem again, but simply go on and execute
potentially unrelated code leading to random errors afterwards.

To fix this, the patch simply goes and re-raises the signal in question
directly from the handler instead of returning from it.  This is done
only on System Z and only for those signals that have this particular
problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 12:22:11 +00:00
Amara Emerson
5d446e61d9 Add support for reading ARM ELF build attributes.
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.

Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 11:36:35 +00:00
Richard Sandiford
820b3fd771 [SystemZ] Add ELF relocation support
Another step towards reinstating the SystemZ backend.  Tests will be
included in the main backend patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 11:11:15 +00:00
Richard Sandiford
0512910867 [SystemZ] Add llvm::Triple::systemz
First step towards reinstating the SystemZ backend.  Tests will be
included in the main backend patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 11:05:17 +00:00
Benjamin Kramer
b9548d8ee3 X86: Add target description for btver2; make autodetection logic aware of AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 10:20:08 +00:00
Pekka Jaaskelainen
555e8f606f Added pocl and TCE blurbs to the ReleaseNotes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181001 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 07:37:04 +00:00
Aaron Ballman
3ff641f222 Unbreaking the non-x86 build bots by protecting the AVX test code properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 02:52:21 +00:00
Aaron Ballman
f57563b61b Correctly testing for AVX support in x86 based off code from Hosts.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 02:39:21 +00:00
Akira Hatanaka
ceb7fb8935 [mips] Remove "Commutative" from property list of non-commutative intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 01:29:31 +00:00
Reid Kleckner
aa35a56975 Fix missing include in Hexagon code for Release+Asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 00:54:56 +00:00
John McCall
26f3bb997f In MC asm parsing, account for the possibility of whitespace within
the "identifier" parsed by the frontend callback by skipping forward
until we've consumed a token that ends at the point dictated by the
callback.

In addition, inform the callback when it's parsing an unevaluated
operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one
(e.g. mov eax, [A::x]).

This commit depends on a clang commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 00:15:41 +00:00
Akira Hatanaka
99ad6ac65e [mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 23:07:05 +00:00
Bill Wendling
53f1b19c6e Remove redundant flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180967 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 22:52:47 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 22:10:59 +00:00
Vincent Lejeune
5ed88013e8 R600: Signed literals are 64bits wide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:53:03 +00:00
Vincent Lejeune
152ebee8f3 R600: If previous bundle is dot4, PV valid chan is always X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:55 +00:00
Vincent Lejeune
e117646f1f R600: Add a test to check that use_kill is emitted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180958 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:46 +00:00
Vincent Lejeune
9e1808733e R600: Improve asmPrint of ALU clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:40 +00:00
Vincent Lejeune
92f24d403f R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:52:30 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:21:57 +00:00
Shuxin Yang
556dd3a9a9 [GV] Remove dead code which is really difficult to decipher.
Actually it took me couple of hours trying to make sense of them and
only to find they are dead code.  I guess the original author used
"allSingleSucc" to indicate if there are any critial edge emanating
from some blocks, and tried to perform code motion (actually speculation)
in the presence of these critical edges; but later on he/she changed mind
and decided to perform edge-splitting first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:14:31 +00:00
Bill Wendling
2900535e65 We don't want FP elimination when doing an Apple-style build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 21:09:03 +00:00
Aaron Ballman
a7a05ee70c Replaced usages of size_type with size_t to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180947 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:30:27 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 20:22:51 +00:00
Richard Sandiford
e2e80cbdcf [mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 18:28:03 +00:00
Manman Ren
436849be6a TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180935 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 18:11:35 +00:00
Adrian Prantl
f9bccc2f1a Provide an API to temporarily suppress DebugLocations from being attached
to emitted instructions.  Use this if you want an instruction to be
counted towards the prologue or if there is no useful source location.

rdar://problem/13442648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 17:27:49 +00:00
Jyotsna Verma
f945d09d53 Hexagon: Honor __builtin_expect by using branch probabilities.
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
  Given a jump opcode return the right pred.new jump opcode with
  a taken vs not-taken hint based on branch probabilities provided
  by the target independent module.
  * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
  * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
  Enhance existing function use branch probabilities like
  HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:39:30 +00:00
Tom Stellard
399880527d R600: Use new tablegen syntax for patterns
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:12 +00:00
Tom Stellard
5ed242c240 R600/SI: remove nonsense select pattern
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 15:30:07 +00:00
Tobias Grosser
66bb622cff Added table of contents declaration in CommandLine Library documentation.
Contributed-by:  Dan Liew <daniel.liew@imperial.ac.uk>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180919 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 14:59:52 +00:00
Michael Liao
299eb2e6e1 80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 09:22:04 +00:00
Michael Liao
db7da200a4 Avoid duplicating logic on frame register selecting when lowering eh_return
No functionality change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 09:18:38 +00:00