Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.
Also take this opportunity to stop creating new Record objects for
synthetic indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.
The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.
Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.
This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.
The root registers can be used to compute the set of overlapping
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.
Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.
This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.
TopoSigs are not currently exposed outside TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
This mapping is for internal use by TableGen. It will not be exposed in
the generated files.
Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.
For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
It is simpler to define a composite index directly:
def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
Than specifying the composite indices on each register:
CompositeIndices = [(ssub_2 dsub_1, ssub_0),
(ssub_3 dsub_1, ssub_1)] in ...
This also makes it clear that SubRegIndex composition is supposed to be
unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.
The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.
It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.
This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
