Tom Stellard 12d43f9baf SelectionDAG: Try to expand all condition codes using getCCSwappedOperands() ...

This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8

2013-09-28 02:50:38 +00:00

..

InstPrinter

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MCTargetDesc

MC: Remove vestigial PCSymbol field from AsmInfo

2013-09-25 09:36:11 +00:00

TargetInfo

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AMDGPU.h

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AMDGPU.td

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AMDGPUAsmPrinter.cpp

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AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUIndirectAddressing.cpp

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AMDGPUInstrInfo.cpp

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AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

R600: Add support for i8 and i16 local memory stores

2013-08-26 15:05:49 +00:00

AMDGPUInstructions.td

R600: Add support for LDS atomic subtract

2013-09-06 20:17:42 +00:00

AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

ISelDAG: spot chain cycles involving MachineNodes

2013-09-22 08:21:56 +00:00

AMDGPUISelLowering.cpp

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

AMDGPUISelLowering.h

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

R600: Fix incorrect LDS size calculation

2013-09-05 18:37:57 +00:00

AMDGPUMCInstLower.cpp

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AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

SelectionDAG: Use correct pointer size when lowering function arguments v2

2013-08-26 15:05:36 +00:00

AMDGPUSubtarget.h

Allow subtarget selection of the default MachineScheduler and document the interface.

2013-09-20 05:14:41 +00:00

AMDGPUTargetMachine.cpp

Allow subtarget selection of the default MachineScheduler and document the interface.

2013-09-20 05:14:41 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

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AMDILBase.td

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AMDILCFGStructurizer.cpp

Add llvm namespace to llvm::next.

2013-09-04 04:26:09 +00:00

AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelLowering.cpp

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AMDILRegisterInfo.td

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CMakeLists.txt

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LLVMBuild.txt

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Makefile

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Processors.td

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R600ControlFlowFinalizer.cpp

R600: Add IsExport bit to TableGen instruction definitions

2013-08-16 01:11:51 +00:00

R600Defines.h

R600: Add support for i8 and i16 local memory stores

2013-08-26 15:05:49 +00:00

R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-09-04 19:53:30 +00:00

R600InstrInfo.cpp

R600: Don't use trans slot for instructions that read LDS source registers

2013-09-12 02:55:06 +00:00

R600InstrInfo.h

R600: Don't use trans slot for instructions that read LDS source registers

2013-09-12 02:55:06 +00:00

R600Instructions.td

SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()

2013-09-28 02:50:38 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()

2013-09-28 02:50:38 +00:00

R600ISelLowering.h

R600: Move fabs/fneg/sel folding logic into PostProcessIsel

2013-09-12 23:44:44 +00:00

R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

R600: Don't use trans slot for instructions that read LDS source registers

2013-09-12 02:55:06 +00:00

R600MachineScheduler.h

R600: Non vector only instruction can be scheduled on trans unit

2013-09-04 19:53:46 +00:00

R600OptimizeVectorRegisters.cpp

R600: Enable folding of inline literals into REQ_SEQUENCE instructions

2013-08-16 01:11:55 +00:00

R600Packetizer.cpp

R600: Don't use trans slot for instructions that read LDS source registers

2013-09-12 02:55:06 +00:00

R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

R600: Don't use trans slot for instructions that read LDS source registers

2013-09-12 02:55:06 +00:00

R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

R600: Coding style

2013-09-05 23:55:13 +00:00

SIAnnotateControlFlow.cpp

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SIDefines.h

R600/SI: Fix broken encoding of DS_WRITE_B32

2013-08-16 16:19:24 +00:00

SIFixSGPRCopies.cpp

R600/SI: Fix another case of illegal VGPR to SGPR copy

2013-08-22 20:21:02 +00:00

SIInsertWaits.cpp

R600/SI: Fix broken encoding of DS_WRITE_B32

2013-08-16 16:19:24 +00:00

SIInstrFormats.td

R600/SI: Fix broken encoding of DS_WRITE_B32

2013-08-16 16:19:24 +00:00

SIInstrInfo.cpp

Remove unused stdio.h includes

2013-08-18 08:29:51 +00:00

SIInstrInfo.h

R600/SI: Fix broken encoding of DS_WRITE_B32

2013-08-16 16:19:24 +00:00

SIInstrInfo.td

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

SIInstructions.td

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

SIIntrinsics.td

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

SIISelLowering.cpp

R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback

2013-09-12 02:55:14 +00:00

SIISelLowering.h

R600/SI: Improve legalization of vector operations

2013-08-14 23:25:00 +00:00

SILowerControlFlow.cpp

R600: Add support for local memory atomic add

2013-09-05 18:38:09 +00:00

SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

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SIRegisterInfo.h

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SIRegisterInfo.td

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SISchedule.td

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SITypeRewriter.cpp

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