Johnny Chen 3cf3059b11 Add a VEXT test. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8

2011-04-07 22:04:01 +00:00

..

arm-tests.txt

Add sanity checking for invalid register encodings for signed/unsigned extend instructions.

2011-04-07 19:28:58 +00:00

dg.exp

…

invalid-CPS2p-arm.txt

Also need to handle invalid imod values for CPS2p.

2011-03-25 17:03:12 +00:00

invalid-CPS3p-arm.txt

Plug a leak in the arm disassembler and put the tests back.

2011-03-24 21:14:28 +00:00

invalid-LDC-form-arm.txt

Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which

2011-03-31 20:54:30 +00:00

invalid-LDRrs-arm.txt

Fix single word and unsigned byte data transfer instruction encodings so that

2011-03-31 19:28:35 +00:00

invalid-LDRT-arm.txt

Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction

2011-04-01 20:21:38 +00:00

invalid-LSL-regform.txt

Add some more comments about checkings of invalid register numbers.

2011-04-07 18:33:19 +00:00

invalid-MCR-arm.txt

A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"

2011-04-06 20:49:02 +00:00

invalid-MOVr-arm.txt

Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.

2011-04-01 23:30:25 +00:00

invalid-MOVs-arm.txt

MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.

2011-04-01 23:15:50 +00:00

invalid-MOVs-LSL-arm.txt

ARM disassembler was erroneously accepting an invalid LSL instruction.

2011-04-05 21:49:44 +00:00

invalid-MSRi-arm.txt

Sanity check MSRi for invalid mask values and reject it as invalid.

2011-04-07 01:37:34 +00:00

invalid-RFEorLDMIA-arm.txt

Fix SRS/SRSW encoding bits.

2011-04-05 00:16:18 +00:00

invalid-RSC-arm.txt

ARM disassembler was erroneously accepting an invalid RSC instruction.

2011-04-05 22:18:07 +00:00

invalid-SMLAD-arm.txt

Should also check SMLAD for invalid register values.

2011-04-07 00:50:25 +00:00

invalid-SRS-arm.txt

Fix SRS/SRSW encoding bits.

2011-04-05 00:16:18 +00:00

invalid-SSAT-arm.txt

Add sanity checking for invalid register encodings for saturating instructions.

2011-04-07 19:02:08 +00:00

invalid-SXTB-arm.txt

Add sanity checking for invalid register encodings for signed/unsigned extend instructions.

2011-04-07 19:28:58 +00:00

invalid-UMAAL-arm.txt

Check for invalid register encodings for UMAAL and friends where:

2011-04-05 17:43:10 +00:00

invalid-VLDMSDB_UPD-arm.txt

Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.

2011-03-29 19:10:06 +00:00

invalid-VQADD-arm.txt

A7.3 register encoding

2011-04-05 22:57:07 +00:00

invalid-VST2b32_UPD-arm.txt

A8.6.393

2011-04-06 22:14:48 +00:00

neon-tests.txt

Add a VEXT test.

2011-04-07 22:04:01 +00:00

thumb-printf.txt

ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.

2011-04-05 19:42:11 +00:00

thumb-tests.txt

A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"

2011-04-06 20:49:02 +00:00