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llvm-6502/lib/Target/R600
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Tom Stellard 58e87a68a8 R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 02:09:45 +00:00
..
InstPrinter
R600: Improve asmPrint of ALU clause
2013-05-02 21:52:40 +00:00
MCTargetDesc
R600: Remove dead code from the CodeEmitter v2
2013-05-06 17:50:57 +00:00
TargetInfo
…
AMDGPU.h
R600: Packetize instructions
2013-04-30 00:14:27 +00:00
AMDGPU.td
…
AMDGPUAsmPrinter.cpp
R600: Emit config values in register / value pairs
2013-05-06 17:50:51 +00:00
AMDGPUAsmPrinter.h
R600: Emit used GPRs count
2013-04-17 15:17:25 +00:00
AMDGPUCallingConv.td
R600/SI: Add support for buffer stores v2
2013-04-05 23:31:51 +00:00
AMDGPUConvertToISA.cpp
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUIndirectAddressing.cpp
…
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
…
AMDGPUInstructions.td
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
2013-05-10 02:09:45 +00:00
AMDGPUIntrinsics.td
…
AMDGPUISelLowering.cpp
…
AMDGPUISelLowering.h
R600/SI: Add support for buffer stores v2
2013-04-05 23:31:51 +00:00
AMDGPUMachineFunction.cpp
R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE
2013-04-26 18:32:24 +00:00
AMDGPUMachineFunction.h
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
AMDGPUMCInstLower.cpp
…
AMDGPUMCInstLower.h
…
AMDGPURegisterInfo.cpp
…
AMDGPURegisterInfo.h
…
AMDGPURegisterInfo.td
…
AMDGPUStructurizeCFG.cpp
…
AMDGPUSubtarget.cpp
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
2013-04-30 00:13:39 +00:00
AMDGPUSubtarget.h
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
2013-04-30 00:13:39 +00:00
AMDGPUTargetMachine.cpp
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
2013-05-10 02:09:45 +00:00
AMDGPUTargetMachine.h
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AMDIL7XXDevice.cpp
…
AMDIL7XXDevice.h
…
AMDIL.h
…
AMDILBase.td
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
2013-04-30 00:13:39 +00:00
AMDILCFGStructurizer.cpp
…
AMDILDevice.cpp
…
AMDILDevice.h
…
AMDILDeviceInfo.cpp
R600: Add some new processor variants
2013-04-30 00:13:27 +00:00
AMDILDeviceInfo.h
…
AMDILDevices.h
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AMDILEvergreenDevice.cpp
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AMDILEvergreenDevice.h
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
…
AMDILIntrinsics.td
…
AMDILISelDAGToDAG.cpp
ArrayRefize getMachineNode(). No functionality change.
2013-04-19 22:22:57 +00:00
AMDILISelLowering.cpp
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AMDILNIDevice.cpp
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AMDILNIDevice.h
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AMDILRegisterInfo.td
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AMDILSIDevice.cpp
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AMDILSIDevice.h
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CMakeLists.txt
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
2013-05-10 02:09:45 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
R600: Clean up comments in Processors.td
2013-05-03 17:21:14 +00:00
R600ControlFlowFinalizer.cpp
R600: Signed literals are 64bits wide
2013-05-02 21:53:03 +00:00
R600Defines.h
R600: Remove dead code from the CodeEmitter v2
2013-05-06 17:50:57 +00:00
R600EmitClauseMarkers.cpp
R600: Fix last ALU of a clause being emitted in a separate clause
2013-04-03 18:24:47 +00:00
R600ExpandSpecialInstrs.cpp
…
R600InstrInfo.cpp
R600: Remove dead code from the CodeEmitter v2
2013-05-06 17:50:57 +00:00
R600InstrInfo.h
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
2013-04-30 00:14:17 +00:00
R600Instructions.td
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
2013-05-10 02:09:45 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
R600: Expand SUB for v2i32/v4i32
2013-05-10 02:09:39 +00:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h
R600: Use .AMDGPU.config section to emit stacksize
2013-04-23 17:34:12 +00:00
R600MachineScheduler.cpp
R600: Factorize maximum alu per clause in a single location
2013-04-03 16:49:34 +00:00
R600MachineScheduler.h
…
R600Packetizer.cpp
R600: If previous bundle is dot4, PV valid chan is always X
2013-05-02 21:52:55 +00:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
R600: Prettier asmPrint of Alu
2013-05-02 21:52:30 +00:00
R600Schedule.td
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
2013-04-30 00:14:17 +00:00
SIAnnotateControlFlow.cpp
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SIDefines.h
R600/SI: Emit config values in register value pairs.
2013-04-15 17:51:35 +00:00
SIInsertWaits.cpp
…
SIInstrFormats.td
R600/SI: Use same names for corresponding MUBUF operands and encoding fields
2013-04-05 23:31:44 +00:00
SIInstrInfo.cpp
R600/SI: dynamical figure out the reg class of MIMG
2013-04-10 08:39:16 +00:00
SIInstrInfo.h
R600/SI: adjust writemask to only the used components
2013-04-10 08:39:08 +00:00
SIInstrInfo.td
R600/SI: Add intrinsic for texture image loading
2013-05-06 23:02:12 +00:00
SIInstructions.td
R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
2013-05-06 23:02:19 +00:00
SIIntrinsics.td
R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
2013-05-06 23:02:19 +00:00
SIISelLowering.cpp
R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
2013-05-06 23:02:15 +00:00
SIISelLowering.h
R600/SI: dynamical figure out the reg class of MIMG
2013-04-10 08:39:16 +00:00
SILowerControlFlow.cpp
…
SIMachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp
…
SIRegisterInfo.h
…
SIRegisterInfo.td
R600/SI: dynamical figure out the reg class of MIMG
2013-04-10 08:39:16 +00:00
SISchedule.td
…