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llvm-6502/test/CodeGen/R600
Tom Stellard 4010e43810 R600/SI: Expand sub for v2i32 and v4i32 for SI
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:37 +00:00
..
128bit-kernel-args.ll
add.ll R600/SI: Expand add for v2i32 and v4i32 2013-06-20 21:55:30 +00:00
alu-split.ll
and.ll
bfe_uint.ll R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 2013-05-10 02:09:45 +00:00
bfi_int.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
call_fs.ll R600: Add a test for r183108 2013-06-04 15:03:35 +00:00
cf_end.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll R600: Const/Neg/Abs can be folded to dot4 2013-06-04 23:17:15 +00:00
elf.ll
elf.r600.ll R600: Emit config values in register / value pairs 2013-05-06 17:50:51 +00:00
fabs.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fadd.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fdiv.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fetch-limits.r600.ll R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
fetch-limits.r700+.ll R600: Fix the fetch limits for R600 generation GPUs 2013-06-07 20:28:55 +00:00
floor.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmad.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmax.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmin.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmul.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
fmul.v4f32.ll
fp_to_sint.ll
fp_to_uint.ll
fsub.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
imm.ll
indirect-addressing.ll R600: Fix calculation of stack offset in AMDGPUFrameLowering 2013-06-07 20:52:05 +00:00
jump-address.ll
kcache-fold.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.imax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.imin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.mul.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
llvm.AMDGPU.tex.ll R600: Swizzle texture/export instructions 2013-06-04 15:04:53 +00:00
llvm.AMDGPU.trunc.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.cos.ll
llvm.pow.ll R600: Schedule copy from phys register at beginning of block 2013-06-05 20:27:35 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 2013-05-08 13:07:29 +00:00
llvm.SI.resinfo.ll R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 2013-05-08 13:07:29 +00:00
llvm.SI.sample.ll
llvm.sin.ll
load-input-fold.ll R600: Lower int_load_input to copyFromReg instead of Register node 2013-05-17 16:51:06 +00:00
load.ll R600/SI: Add support for global loads 2013-06-03 17:39:43 +00:00
load.vec.ll R600: Expand v2i32 load/store instead of custom lowering 2013-06-20 21:55:23 +00:00
loop-address.ll
lshl.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
lshr.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
mul.ll R600: Expand MUL for v4i32/v2i32 2013-05-10 02:09:34 +00:00
mulhu.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
or.ll
predicates.ll
pv-packing.ll R600: PV stores Reg id, not index 2013-06-17 20:16:40 +00:00
pv.ll R600: use capital letter for PV channel 2013-06-03 15:44:35 +00:00
r600-encoding.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
README
reciprocal.ll
rotr.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
rv7x0_count3.ll R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 2013-06-17 20:16:26 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
set-dx10.ll
setcc.ll
seto.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
setuo.ll R600/SI: Add a calling convention for compute shaders 2013-06-03 17:40:11 +00:00
shl.ll R600/SI: Add patterns for 64-bit shift operations 2013-05-20 15:02:12 +00:00
short-args.ll
sign_extend.ll R600/SI: Custom lower i64 sign_extend 2013-06-03 17:40:03 +00:00
sint_to_fp.ll
sra.ll R600: Expand SRA for v4i32/v2i32 2013-05-10 02:09:29 +00:00
srl.ll
store.ll R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 2013-06-14 22:12:24 +00:00
store.r600.ll
sub.ll R600/SI: Expand sub for v2i32 and v4i32 for SI 2013-06-20 21:55:37 +00:00
tex-clause-antidep.ll R600: Anti dep better handled in tex clause 2013-06-07 23:30:26 +00:00
texture-input-merge.ll R600: Add a pass that merge Vector Register 2013-06-05 21:38:04 +00:00
udiv.ll
uint_to_fp.ll
uitofp.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
unsupported-cc.ll
urecip.ll
urem.ll
vertex-fetch-encoding.ll R600: Use correct encoding for Vertex Fetch instructions on Cayman 2013-06-14 22:12:30 +00:00
vselect.ll R600: use capital letter for PV channel 2013-06-03 15:44:35 +00:00
vtx-schedule.ll R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 2013-05-23 18:26:42 +00:00
work-item-intrinsics.ll R600/SI: Add support for work item and work group intrinsics 2013-06-03 17:40:18 +00:00
xor.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.