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5f3a6430d6
llvm-6502/lib/Target/R600
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Matt Arsenault 5f3a6430d6 Add address space argument to isLegalAddressingMode 
This is important because of different addressing modes
depending on the address space for GPU targets.

This only adds the argument, and does not update
any of the uses to provide the correct address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238723 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 05:31:59 +00:00
..
AsmParser MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
InstPrinter R600/SI: Initial support for assembler and inline assembly 2015-04-08 01:09:26 +00:00
MCTargetDesc Use std::bitset for SubtargetFeatures. 2015-05-26 10:47:10 +00:00
TargetInfo
AMDGPU.h R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
AMDGPU.td R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
AMDGPUAlwaysInlinePass.cpp R600: Fix always inline pass breaking noinline functions 2015-04-22 17:10:44 +00:00
AMDGPUAsmPrinter.cpp Move alignment from MCSectionData to MCSection. 2015-05-21 19:20:38 +00:00
AMDGPUAsmPrinter.h R600/SI: Add some missing overrides 2015-04-08 02:07:05 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
AMDGPUFrameLowering.h [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
AMDGPUInstrInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPUInstrInfo.h ArrayRefize memory operand folding. NFC. 2015-02-28 12:04:00 +00:00
AMDGPUInstrInfo.td R600/SI: Remove explicit m0 operand from v_interp instructions 2015-05-12 15:00:46 +00:00
AMDGPUInstructions.td R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32 2015-03-04 17:33:45 +00:00
AMDGPUISelDAGToDAG.cpp R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
AMDGPUISelLowering.cpp R600: Add comments to subword private address load lowering code 2015-05-26 18:07:21 +00:00
AMDGPUISelLowering.h Add target hook to allow merging stores of nonzero constants 2015-05-24 00:51:27 +00:00
AMDGPUMachineFunction.cpp R600: Canonicalize access to function attributes, NFC 2015-02-14 02:45:45 +00:00
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only 2015-05-18 22:13:54 +00:00
AMDGPURegisterInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPURegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
AMDGPUSubtarget.h R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
AMDGPUTargetMachine.cpp R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
AMDGPUTargetMachine.h Remove the target independent TargetMachine::getSubtarget and 2015-03-21 04:22:23 +00:00
AMDGPUTargetTransformInfo.cpp [X86] Disable loop unrolling in loop vectorization pass when VF is 1. 2015-05-06 17:12:25 +00:00
AMDGPUTargetTransformInfo.h [X86] Disable loop unrolling in loop vectorization pass when VF is 1. 2015-05-06 17:12:25 +00:00
AMDILCFGStructurizer.cpp CodeGen: Use the new DebugLoc API, NFC 2015-03-30 19:14:47 +00:00
AMDKernelCodeT.h
CaymanInstructions.td R600/SI: Implement correct f64 fdiv 2015-02-14 04:30:08 +00:00
CIInstructions.td R600/SI: Add assembler support for all CI and VI VOP1 instructions 2015-04-23 19:33:54 +00:00
CMakeLists.txt R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
EvergreenInstructions.td Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
LLVMBuild.txt
Makefile
Processors.td R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
R600ClauseMergePass.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
R600ControlFlowFinalizer.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600InstrInfo.h
R600Instructions.td R600: Make FMIN/MAXNUM legal on all asics 2015-04-12 23:45:05 +00:00
R600Intrinsics.td
R600ISelLowering.cpp R600: Rely on TypeLegalizer to use divrem instead of div/rem 2015-05-27 16:54:10 +00:00
R600ISelLowering.h Reinstate revisions r234755, r234759, r234760 2015-04-30 17:15:56 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp Remove a few more calls to TargetMachine::getSubtarget from the 2015-02-19 01:10:55 +00:00
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
R600Packetizer.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
R600RegisterInfo.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600RegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp Reduce dyn_cast<> to isa<> or cast<> where possible. 2015-04-10 11:24:51 +00:00
R700Instructions.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:24:40 +00:00
SIAnnotateControlFlow.cpp R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass 2015-05-01 03:44:08 +00:00
SIDefines.h R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIFixControlFlowLiveIntervals.cpp R600/SI: add pass to mark CF live ranges as non-spillable 2015-05-12 17:13:02 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove M0Reg register class 2015-05-12 15:00:52 +00:00
SIFixSGPRLiveRanges.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
SIFoldOperands.cpp R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg) 2015-05-12 14:18:11 +00:00
SIInsertWaits.cpp Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
SIInstrFormats.td R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIInstrInfo.cpp R600/SI: Fix verifier error when producing v_madmk_f32 2015-04-24 01:57:58 +00:00
SIInstrInfo.h R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIInstrInfo.td R600/SI: Add assembler support for all CI and VI VOP2 instructions 2015-05-26 15:55:52 +00:00
SIInstructions.td R600/SI: Add assembler support for all CI and VI VOP2 instructions 2015-05-26 15:55:52 +00:00
SIIntrinsics.td
SIISelLowering.cpp Add address space argument to isLegalAddressingMode 2015-06-01 05:31:59 +00:00
SIISelLowering.h Add address space argument to isLegalAddressingMode 2015-06-01 05:31:59 +00:00
SILoadStoreOptimizer.cpp R600/SI: Remove explicit m0 operand from DS instructions 2015-05-12 15:00:49 +00:00
SILowerControlFlow.cpp R600/SI: Fix indirect addressing with a negative constant offset 2015-04-23 20:32:01 +00:00
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp Remove a few more calls to TargetMachine::getSubtarget from the 2015-02-19 01:10:55 +00:00
SIMachineFunctionInfo.h
SIPrepareScratchRegs.cpp R600/SI: Fix bug in VGPR spilling 2015-05-12 18:59:17 +00:00
SIRegisterInfo.cpp R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0 2015-05-12 15:00:53 +00:00
SIRegisterInfo.h Remove the need to cache the subtarget in the R600 TargetRegisterInfo 2015-03-11 18:43:21 +00:00
SIRegisterInfo.td R600/SI: Remove M0Reg register class 2015-05-12 15:00:52 +00:00
SISchedule.td
SIShrinkInstructions.cpp Purge unused includes throughout libSupport. 2015-03-23 18:07:13 +00:00
SITypeRewriter.cpp Remove more superfluous .str() and replace std::string concatenation with Twine. 2015-03-30 15:42:36 +00:00
VIInstrFormats.td R600/SI: Rename dst encoding field to be consistent with docs 2015-02-18 02:15:37 +00:00
VIInstructions.td R600/SI: Add assembler support for all CI and VI VOP2 instructions 2015-05-26 15:55:52 +00:00