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AsmParser
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MC: Clean up MCExpr naming. NFC.
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2015-05-30 01:25:56 +00:00 |
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InstPrinter
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R600/SI: Initial support for assembler and inline assembly
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2015-04-08 01:09:26 +00:00 |
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MCTargetDesc
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Use std::bitset for SubtargetFeatures.
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2015-05-26 10:47:10 +00:00 |
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TargetInfo
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AMDGPU.h
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R600/SI: add pass to mark CF live ranges as non-spillable
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2015-05-12 17:13:02 +00:00 |
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AMDGPU.td
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R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
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2015-05-25 16:15:54 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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R600: Fix always inline pass breaking noinline functions
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2015-04-22 17:10:44 +00:00 |
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AMDGPUAsmPrinter.cpp
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Move alignment from MCSectionData to MCSection.
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2015-05-21 19:20:38 +00:00 |
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AMDGPUAsmPrinter.h
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R600/SI: Add some missing overrides
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2015-04-08 02:07:05 +00:00 |
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AMDGPUCallingConv.td
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AMDGPUFrameLowering.cpp
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[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
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2015-05-05 17:38:16 +00:00 |
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AMDGPUFrameLowering.h
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[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
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2015-05-05 17:38:16 +00:00 |
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AMDGPUInstrInfo.cpp
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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R600/SI: Remove explicit m0 operand from v_interp instructions
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2015-05-12 15:00:46 +00:00 |
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AMDGPUInstructions.td
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R600/SI: Remove explicit m0 operand from DS instructions
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2015-05-12 15:00:49 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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R600/SI: Remove explicit m0 operand from DS instructions
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2015-05-12 15:00:49 +00:00 |
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AMDGPUISelLowering.cpp
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R600: Add comments to subword private address load lowering code
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2015-05-26 18:07:21 +00:00 |
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AMDGPUISelLowering.h
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Add target hook to allow merging stores of nonzero constants
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2015-05-24 00:51:27 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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MC: Clean up MCExpr naming. NFC.
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2015-05-30 01:25:56 +00:00 |
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AMDGPUMCInstLower.h
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AMDGPUPromoteAlloca.cpp
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Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only
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2015-05-18 22:13:54 +00:00 |
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AMDGPURegisterInfo.cpp
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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AMDGPURegisterInfo.h
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
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2015-05-25 16:15:54 +00:00 |
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AMDGPUSubtarget.h
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R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
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2015-05-25 16:15:54 +00:00 |
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AMDGPUTargetMachine.cpp
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R600/SI: add pass to mark CF live ranges as non-spillable
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2015-05-12 17:13:02 +00:00 |
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AMDGPUTargetMachine.h
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Remove the target independent TargetMachine::getSubtarget and
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2015-03-21 04:22:23 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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[X86] Disable loop unrolling in loop vectorization pass when VF is 1.
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2015-05-06 17:12:25 +00:00 |
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AMDGPUTargetTransformInfo.h
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[X86] Disable loop unrolling in loop vectorization pass when VF is 1.
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2015-05-06 17:12:25 +00:00 |
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AMDILCFGStructurizer.cpp
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CodeGen: Use the new DebugLoc API, NFC
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2015-03-30 19:14:47 +00:00 |
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AMDKernelCodeT.h
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CaymanInstructions.td
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CIInstructions.td
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R600/SI: Add assembler support for all CI and VI VOP1 instructions
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2015-04-23 19:33:54 +00:00 |
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CMakeLists.txt
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R600/SI: add pass to mark CF live ranges as non-spillable
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2015-05-12 17:13:02 +00:00 |
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EvergreenInstructions.td
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Reinstate revisions r234755, r234759, r234760
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2015-04-30 17:15:56 +00:00 |
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LLVMBuild.txt
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Makefile
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Processors.td
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R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
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2015-05-25 16:15:54 +00:00 |
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R600ClauseMergePass.cpp
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Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.
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2015-03-23 19:32:43 +00:00 |
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600InstrInfo.cpp
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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R600InstrInfo.h
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R600Instructions.td
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R600: Make FMIN/MAXNUM legal on all asics
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2015-04-12 23:45:05 +00:00 |
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R600Intrinsics.td
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R600ISelLowering.cpp
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R600: Rely on TypeLegalizer to use divrem instead of div/rem
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2015-05-27 16:54:10 +00:00 |
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R600ISelLowering.h
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Reinstate revisions r234755, r234759, r234760
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2015-04-30 17:15:56 +00:00 |
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.
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2015-03-23 19:32:43 +00:00 |
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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R600RegisterInfo.h
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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Reduce dyn_cast<> to isa<> or cast<> where possible.
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2015-04-10 11:24:51 +00:00 |
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
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2015-05-01 03:44:08 +00:00 |
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SIDefines.h
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R600/SI: Fix bug in VGPR spilling
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2015-05-12 18:59:17 +00:00 |
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SIFixControlFlowLiveIntervals.cpp
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R600/SI: add pass to mark CF live ranges as non-spillable
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2015-05-12 17:13:02 +00:00 |
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SIFixSGPRCopies.cpp
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R600/SI: Remove M0Reg register class
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2015-05-12 15:00:52 +00:00 |
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SIFixSGPRLiveRanges.cpp
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Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.
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2015-03-23 19:32:43 +00:00 |
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SIFoldOperands.cpp
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R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)
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2015-05-12 14:18:11 +00:00 |
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SIInsertWaits.cpp
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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SIInstrFormats.td
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R600/SI: Fix bug in VGPR spilling
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2015-05-12 18:59:17 +00:00 |
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SIInstrInfo.cpp
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R600/SI: Fix verifier error when producing v_madmk_f32
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2015-04-24 01:57:58 +00:00 |
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SIInstrInfo.h
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R600/SI: Fix bug in VGPR spilling
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2015-05-12 18:59:17 +00:00 |
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SIInstrInfo.td
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R600/SI: Add assembler support for all CI and VI VOP2 instructions
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2015-05-26 15:55:52 +00:00 |
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SIInstructions.td
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R600/SI: Add assembler support for all CI and VI VOP2 instructions
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2015-05-26 15:55:52 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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R600/SI: Don't hardcode pointer type
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2015-06-01 21:58:24 +00:00 |
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SIISelLowering.h
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Add address space argument to isLegalAddressingMode
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2015-06-01 05:31:59 +00:00 |
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SILoadStoreOptimizer.cpp
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R600/SI: Remove explicit m0 operand from DS instructions
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2015-05-12 15:00:49 +00:00 |
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SILowerControlFlow.cpp
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R600/SI: Fix indirect addressing with a negative constant offset
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2015-04-23 20:32:01 +00:00 |
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIPrepareScratchRegs.cpp
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R600/SI: Fix bug in VGPR spilling
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2015-05-12 18:59:17 +00:00 |
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SIRegisterInfo.cpp
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R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0
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2015-05-12 15:00:53 +00:00 |
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SIRegisterInfo.h
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Remove the need to cache the subtarget in the R600 TargetRegisterInfo
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2015-03-11 18:43:21 +00:00 |
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SIRegisterInfo.td
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R600/SI: Remove M0Reg register class
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2015-05-12 15:00:52 +00:00 |
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SISchedule.td
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SIShrinkInstructions.cpp
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Purge unused includes throughout libSupport.
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2015-03-23 18:07:13 +00:00 |
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SITypeRewriter.cpp
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Remove more superfluous .str() and replace std::string concatenation with Twine.
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2015-03-30 15:42:36 +00:00 |
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VIInstrFormats.td
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VIInstructions.td
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R600/SI: Add assembler support for all CI and VI VOP2 instructions
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2015-05-26 15:55:52 +00:00 |
