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doing global variable classification anymore) and hookized, sink almost all target targets global variable emission code into AsmPrinter and out of each target. Some notes: 1. PIC16 does completely custom and crazy stuff, so it is not changed. 2. XCore has some custom handling for extra directives. I'll look at it next. 3. This switches linux/ppc to use .globl instead of .global. If .globl is actually wrong, let me know and I'll fix it. 4. This makes linux/ppc get a lot of random cases right which were obviously wrong before, it is probably now a bit healthier. 5. Blackfin will probably start getting .comm and other things that it didn't before. If this is undesirable, it should explicitly opt out of these things by clearing the relevant fields of MCAsmInfo. This leads to a nice diffstat: 14 files changed, 127 insertions(+), 830 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93858 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
AsmPrinter | ||
TargetInfo | ||
CMakeLists.txt | ||
DelaySlotFiller.cpp | ||
FPMover.cpp | ||
Makefile | ||
README.txt | ||
Sparc.h | ||
Sparc.td | ||
SparcCallingConv.td | ||
SparcInstrFormats.td | ||
SparcInstrInfo.cpp | ||
SparcInstrInfo.h | ||
SparcInstrInfo.td | ||
SparcISelDAGToDAG.cpp | ||
SparcISelLowering.cpp | ||
SparcISelLowering.h | ||
SparcMachineFunctionInfo.h | ||
SparcMCAsmInfo.cpp | ||
SparcMCAsmInfo.h | ||
SparcRegisterInfo.cpp | ||
SparcRegisterInfo.h | ||
SparcRegisterInfo.td | ||
SparcSubtarget.cpp | ||
SparcSubtarget.h | ||
SparcTargetMachine.cpp | ||
SparcTargetMachine.h |
To-do ----- * Keep the address of the constant pool in a register instead of forming its address all of the time. * We can fold small constant offsets into the %hi/%lo references to constant pool addresses as well. * When in V9 mode, register allocate %icc[0-3]. * Add support for isel'ing UMUL_LOHI instead of marking it as Expand. * Emit the 'Branch on Integer Register with Prediction' instructions. It's not clear how to write a pattern for this though: float %t1(int %a, int* %p) { %C = seteq int %a, 0 br bool %C, label %T, label %F T: store int 123, int* %p br label %F F: ret float undef } codegens to this: t1: save -96, %o6, %o6 1) subcc %i0, 0, %l0 1) bne .LBBt1_2 ! F nop .LBBt1_1: ! T or %g0, 123, %l0 st %l0, [%i1] .LBBt1_2: ! F restore %g0, %g0, %g0 retl nop 1) should be replaced with a brz in V9 mode. * Same as above, but emit conditional move on register zero (p192) in V9 mode. Testcase: int %t1(int %a, int %b) { %C = seteq int %a, 0 %D = select bool %C, int %a, int %b ret int %D } * Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling with the Y register, if they are faster. * Codegen bswap(load)/store(bswap) -> load/store ASI * Implement frame pointer elimination, e.g. eliminate save/restore for leaf fns. * Fill delay slots