David Majnemer 8ba3f9c900 MC: Remove vestigial PCSymbol field from AsmInfo ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191362 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-25 09:36:11 +00:00
..
InstPrinter
MCTargetDesc	MC: Remove vestigial PCSymbol field from AsmInfo	2013-09-25 09:36:11 +00:00
TargetInfo
AMDGPU.h	R600/SI: Convert v16i8 resource descriptors to i128	2013-08-14 23:24:45 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	R600: Add support for i8 and i16 local memory stores	2013-08-26 15:05:49 +00:00
AMDGPUInstructions.td	R600: Add support for LDS atomic subtract	2013-09-06 20:17:42 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp	ISelDAG: spot chain cycles involving MachineNodes	2013-09-22 08:21:56 +00:00
AMDGPUISelLowering.cpp	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUISelLowering.h	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h	R600: Fix incorrect LDS size calculation	2013-09-05 18:37:57 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.h	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp	SelectionDAG: Use correct pointer size when lowering function arguments v2	2013-08-26 15:05:36 +00:00
AMDGPUSubtarget.h	Allow subtarget selection of the default MachineScheduler and document the interface.	2013-09-20 05:14:41 +00:00
AMDGPUTargetMachine.cpp	Allow subtarget selection of the default MachineScheduler and document the interface.	2013-09-20 05:14:41 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILBase.td
AMDILCFGStructurizer.cpp	Add llvm namespace to llvm::next.	2013-09-04 04:26:09 +00:00
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp
AMDILRegisterInfo.td
CMakeLists.txt	R600/SI: Convert v16i8 resource descriptors to i128	2013-08-14 23:24:45 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ControlFlowFinalizer.cpp	R600: Add IsExport bit to TableGen instruction definitions	2013-08-16 01:11:51 +00:00
R600Defines.h	R600: Add support for i8 and i16 local memory stores	2013-08-26 15:05:49 +00:00
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td	R600: Use SchedModel enum for is{Trans,Vector}Only functions	2013-09-04 19:53:30 +00:00
R600InstrInfo.cpp	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600InstrInfo.h	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600Instructions.td	R600: Add support for LDS atomic subtract	2013-09-06 20:17:42 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Move clamp handling code to R600IselLowering.cpp	2013-09-12 23:45:00 +00:00
R600ISelLowering.h	R600: Move fabs/fneg/sel folding logic into PostProcessIsel	2013-09-12 23:44:44 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600MachineScheduler.h	R600: Non vector only instruction can be scheduled on trans unit	2013-09-04 19:53:46 +00:00
R600OptimizeVectorRegisters.cpp	R600: Enable folding of inline literals into REQ_SEQUENCE instructions	2013-08-16 01:11:55 +00:00
R600Packetizer.cpp	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600RegisterInfo.cpp	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
R600RegisterInfo.h	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
R600RegisterInfo.td	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp	R600: Coding style	2013-09-05 23:55:13 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h	R600/SI: Fix broken encoding of DS_WRITE_B32	2013-08-16 16:19:24 +00:00
SIFixSGPRCopies.cpp	R600/SI: Fix another case of illegal VGPR to SGPR copy	2013-08-22 20:21:02 +00:00
SIInsertWaits.cpp	R600/SI: Fix broken encoding of DS_WRITE_B32	2013-08-16 16:19:24 +00:00
SIInstrFormats.td	R600/SI: Fix broken encoding of DS_WRITE_B32	2013-08-16 16:19:24 +00:00
SIInstrInfo.cpp	Remove unused stdio.h includes	2013-08-18 08:29:51 +00:00
SIInstrInfo.h	R600/SI: Fix broken encoding of DS_WRITE_B32	2013-08-16 16:19:24 +00:00
SIInstrInfo.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIInstructions.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIIntrinsics.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIISelLowering.cpp	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIISelLowering.h	R600/SI: Improve legalization of vector operations	2013-08-14 23:25:00 +00:00
SILowerControlFlow.cpp	R600: Add support for local memory atomic add	2013-09-05 18:38:09 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp	R600/SI: Choose the correct MOV instruction for copying immediates	2013-08-14 23:24:24 +00:00
SIRegisterInfo.h	R600/SI: Choose the correct MOV instruction for copying immediates	2013-08-14 23:24:24 +00:00
SIRegisterInfo.td	R600/SI: Convert v16i8 resource descriptors to i128	2013-08-14 23:24:45 +00:00
SISchedule.td
SITypeRewriter.cpp	R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics	2013-08-14 23:24:53 +00:00