llvm-6502/test/CodeGen/R600
Tom Stellard 81c6c9690a R600/SI: Enable selecting SALU inside branches
We can do this now that the FixSGPRLiveRanges pass is working.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-24 01:33:28 +00:00
..
32-bit-local-address-space.ll R600/SI: Use a ComplexPattern for DS loads and stores 2014-08-22 18:49:33 +00:00
64bit-kernel-args.ll
128bit-kernel-args.ll
add_i64.ll R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operations 2014-09-05 14:07:59 +00:00
add-debug.ll Fix classof for ISD::INTRINSIC_W_CHAIN and INTRINSIC_VOID 2014-08-13 01:15:37 +00:00
add.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
address-space.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
and.ll R600/SI: Prefer selecting more e64 instruction forms. 2014-09-15 17:15:02 +00:00
anyext.ll
array-ptr-calc-i32.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
array-ptr-calc-i64.ll R600/SI: Un-xfail tests which work now 2014-09-19 23:02:18 +00:00
atomic_cmp_swap_local.ll R600/SI: Replace LDS atomics with no return versions 2014-09-08 15:07:31 +00:00
atomic_load_add.ll R600/SI: Replace LDS atomics with no return versions 2014-09-08 15:07:31 +00:00
atomic_load_sub.ll R600/SI: Replace LDS atomics with no return versions 2014-09-08 15:07:31 +00:00
basic-branch.ll
basic-loop.ll
bfe_uint.ll
bfi_int.ll R600/SI: Prefer selecting more e64 instruction forms. 2014-09-15 17:15:02 +00:00
big_alu.ll
bitcast.ll
bswap.ll
build_vector.ll
call_fs.ll
call.ll
cayman-loop-bug.ll
cf_end.ll
cf-stack-bug.ll
codegen-prepare-addrmode-sext.ll R600/SI: Try to keep i32 mul on SALU 2014-09-03 23:24:35 +00:00
combine_vloads.ll
complex-folding.ll
concat_vectors.ll R600/SI: Custom lower CONCAT_VECTORS 2014-08-09 01:06:56 +00:00
copy-illegal-type.ll
ctlz_zero_undef.ll
ctpop64.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
ctpop.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
cttz_zero_undef.ll
cvt_f32_ubyte.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
default-fp-mode.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
ds-negative-offset-addressing-mode-loop.ll R600/SI: Use a ComplexPattern for DS loads and stores 2014-08-22 18:49:33 +00:00
elf.ll
elf.r600.ll
extload.ll R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant 2014-08-11 22:18:17 +00:00
extract_vector_elt_i16.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
fabs.f64.ll R600/SI: Use source modifier for f64 fabs 2014-08-15 18:42:15 +00:00
fabs.ll R600/SI: Move all fabs / fneg handling to patterns 2014-08-15 18:42:22 +00:00
fadd64.ll
fadd.ll R600: Cleanup fadd and fsub tests 2014-08-06 20:27:55 +00:00
fceil64.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fconst64.ll
fcopysign.f32.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
fcopysign.f64.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
fdiv64.ll
fdiv.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
flat-address-space.ll R600/SI: Add preliminary support for flat address space 2014-09-15 15:41:53 +00:00
floor.ll
fma.f64.ll
fma.ll
fmad.ll
fmax.ll
fmin.ll
fmul64.ll R600/SI: Make sure double vector fmul is tested 2014-09-15 17:04:54 +00:00
fmul.ll Fix interference caused by fmul 2, x -> fadd x, x 2014-09-02 19:02:53 +00:00
fmuladd.ll
fnearbyint.ll
fneg-fabs.f64.ll R600/SI: Move all fabs / fneg handling to patterns 2014-08-15 18:42:22 +00:00
fneg-fabs.ll R600/SI: Move all fabs / fneg handling to patterns 2014-08-15 18:42:22 +00:00
fneg.f64.ll R600/SI: Use source modifiers for f64 fneg 2014-08-15 18:42:18 +00:00
fneg.ll R600/SI: Change formatting of printed FP immediates 2014-09-17 17:32:13 +00:00
fp16_to_fp.ll
fp32_to_fp16.ll
fp64_to_sint.ll
fp_to_sint.ll [SDAG] When performing post-legalize DAG combining, run the legalizer 2014-07-26 05:49:40 +00:00
fp_to_uint.f64.ll
fp_to_uint.ll [SDAG] When performing post-legalize DAG combining, run the legalizer 2014-07-26 05:49:40 +00:00
fpext.ll
fptrunc.ll
frem.ll R600: Custom lower frem 2014-09-10 21:44:27 +00:00
fsqrt.ll
fsub64.ll
fsub.ll R600: Cleanup fadd and fsub tests 2014-08-06 20:27:55 +00:00
ftrunc.ll
gep-address-space.ll R600/SI: Use a ComplexPattern for DS loads and stores 2014-08-22 18:49:33 +00:00
gv-const-addrspace-fail.ll R600/SI: Un xfail a test that works now 2014-09-19 22:42:40 +00:00
gv-const-addrspace.ll
half.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
imm.ll R600/SI: Change formatting of printed FP immediates 2014-09-17 17:32:13 +00:00
indirect-addressing-si.ll
indirect-private-64.ll
infinite-loop-evergreen.ll
infinite-loop.ll
input-mods.ll
insert_vector_elt.ll R600/SI: Un-xfail tests which work now 2014-09-19 23:02:18 +00:00
jump-address.ll
kcache-fold.ll
kernel-args.ll R600: Correctly set the src value offset for scalarized kernel args 2014-08-13 18:14:11 +00:00
large-alloca.ll
large-constant-initializer.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.abs.ll
llvm.AMDGPU.barrier.global.ll
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.bfe.i32.ll R600: Better fix for bug 20982 2014-09-19 00:42:06 +00:00
llvm.AMDGPU.bfe.u32.ll
llvm.AMDGPU.bfi.ll
llvm.AMDGPU.bfm.ll
llvm.AMDGPU.brev.ll
llvm.AMDGPU.clamp.ll
llvm.AMDGPU.cube.ll
llvm.AMDGPU.cvt_f32_ubyte.ll
llvm.AMDGPU.div_fixup.ll
llvm.AMDGPU.div_fmas.ll
llvm.AMDGPU.div_scale.ll
llvm.amdgpu.dp4.ll
llvm.AMDGPU.fract.ll
llvm.AMDGPU.imad24.ll
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.imul24.ll
llvm.AMDGPU.kill.ll
llvm.amdgpu.kilp.ll
llvm.AMDGPU.ldexp.ll R600/SI: Add intrinsic for ldexp 2014-08-15 17:30:25 +00:00
llvm.AMDGPU.legacy.rsq.ll
llvm.amdgpu.lrp.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.rcp.f64.ll
llvm.AMDGPU.rcp.ll
llvm.AMDGPU.rsq.clamped.f64.ll
llvm.AMDGPU.rsq.clamped.ll
llvm.AMDGPU.rsq.ll R600/SI: Prefer selecting more e64 instruction forms. 2014-09-15 17:15:02 +00:00
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trig_preop.ll
llvm.AMDGPU.trunc.ll
llvm.AMDGPU.umad24.ll
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.AMDGPU.umul24.ll
llvm.cos.ll
llvm.exp2.ll
llvm.floor.ll
llvm.log2.ll
llvm.memcpy.ll R600: Increase nearby load scheduling threshold. 2014-08-06 00:29:49 +00:00
llvm.pow.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.ll R600: Fix FROUND 2014-09-05 14:26:54 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.gather4.ll
llvm.SI.getlod.ll
llvm.SI.image.ll
llvm.SI.image.sample.ll
llvm.SI.image.sample.o.ll
llvm.SI.imageload.ll
llvm.SI.load.dword.ll
llvm.SI.resinfo.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
llvm.SI.sample-masked.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll
llvm.SI.sendmsg.ll
llvm.SI.tbuffer.store.ll
llvm.SI.tid.ll
llvm.sin.ll R600/SI: Change formatting of printed FP immediates 2014-09-17 17:32:13 +00:00
llvm.sqrt.ll
llvm.trunc.ll
load64.ll
load-i1.ll
load-input-fold.ll
load.ll
load.vec.ll
local-64.ll R600/SI: Use a ComplexPattern for DS loads and stores 2014-08-22 18:49:33 +00:00
local-atomics64.ll R600/SI: Replace LDS atomics with no return versions 2014-09-08 15:07:31 +00:00
local-atomics.ll R600: Test local atomics for evergreen 2014-09-11 15:02:52 +00:00
local-memory-two-objects.ll R600/SI: Use a ComplexPattern for DS loads and stores 2014-08-22 18:49:33 +00:00
local-memory.ll
loop-address.ll
loop-idiom.ll
lshl.ll
lshr.ll
mad_int24.ll
mad_uint24.ll
mad-sub.ll R600/SI: Use mad for fsub + fmul 2014-08-29 16:01:14 +00:00
max-literals.ll
missing-store.ll R600/SI: Fix losing chain when fixing reg class of loads. 2014-09-10 23:26:19 +00:00
mubuf.ll R600/SI: Add some mubuf testcases. 2014-09-15 16:48:01 +00:00
mul_int24.ll
mul_uint24.ll R600/SI: Do abs/neg folding with ComplexPatterns 2014-08-01 00:32:39 +00:00
mul.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
mulhu.ll
no-initializer-constant-addrspace.ll
operand-spacing.ll R600/SI: Fix extra whitespace in asm str 2014-08-03 05:27:14 +00:00
or.ll R600/SI: Fix hardcoded register numbers in test 2014-09-02 20:43:07 +00:00
packetizer.ll
parallelandifcollapse.ll R600: Un-xfail a test which passes with pass disabled 2014-09-19 23:02:20 +00:00
parallelorifcollapse.ll
predicate-dp4.ll
predicates.ll
private-memory-atomics.ll
private-memory-broken.ll
private-memory.ll R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant 2014-08-11 22:18:17 +00:00
pv-packing.ll
pv.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600cfg.ll
README
reciprocal.ll
register-count-comments.ll R600/SI: Fix off by 1 error in used register count 2014-09-11 22:51:37 +00:00
reorder-stores.ll
rotl.i64.ll R600/SI: Relax some ordering in tests. 2014-09-02 21:45:50 +00:00
rotl.ll R600/SI: Relax some ordering in tests. 2014-09-02 21:45:50 +00:00
rotr.i64.ll R600/SI: Relax a few tests to help enable scheduler 2014-09-06 20:44:41 +00:00
rotr.ll
rsq.ll R600/SI: Prefer selecting more e64 instruction forms. 2014-09-15 17:15:02 +00:00
rv7x0_count3.ll
saddo.ll
salu-to-valu.ll R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions 2014-08-21 20:41:00 +00:00
scalar_to_vector.ll
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant 2014-08-11 22:18:17 +00:00
schedule-if-2.ll
schedule-if.ll
schedule-kernel-arg-loads.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
sdivrem24.ll R600: Use i24 optimized path for SREM 2014-08-12 17:31:17 +00:00
select64.ll
select-i1.ll
select-vectors.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
set-dx10.ll
setcc64.ll
setcc-equivalent.ll [SDAG] When performing post-legalize DAG combining, run the legalizer 2014-07-26 05:49:40 +00:00
setcc-opt.ll
setcc.ll
seto.ll
setuo.ll
sext-in-reg.ll R600/SI: Relax some ordering in tests. 2014-09-02 21:45:50 +00:00
sgpr-control-flow.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
shared-op-cycle.ll
shl_add_constant.ll Add DAG combine for shl + add of constants. 2014-09-11 17:34:19 +00:00
shl_add_ptr.ll Add DAG combine for shl + add of constants. 2014-09-11 17:34:19 +00:00
shl.ll
si-annotate-cf-assertion.ll
si-lod-bias.ll
si-sgpr-spill.ll
si-vector-hang.ll
sign_extend.ll R600/SI: Try to keep i32 mul on SALU 2014-09-03 23:24:35 +00:00
simplify-demanded-bits-build-pair.ll
sint_to_fp64.ll
sint_to_fp.ll
smrd.ll R600/SI: Fix test to prepare for scheduler 2014-09-19 18:11:16 +00:00
split-scalar-i64-add.ll R600/SI: Add failing testcase. 2014-09-02 19:12:31 +00:00
sra.ll
srem.ll
srl.ll
ssubo.ll R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operations 2014-09-05 14:07:59 +00:00
store-v3i32.ll
store-v3i64.ll
store-vector-ptrs.ll R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the function 2014-08-21 20:40:58 +00:00
store.ll
store.r600.ll
structurize1.ll
structurize.ll
sub.ll R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operations 2014-09-05 14:07:59 +00:00
swizzle-export.ll
tex-clause-antidep.ll
texture-input-merge.ll
trunc-store-i1.ll
trunc-vector-store-assertion-failure.ll
trunc.ll R600/SI: Prefer selecting more e64 instruction forms. 2014-09-15 17:15:02 +00:00
uaddo.ll R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operations 2014-09-05 14:07:59 +00:00
udiv.ll
udivrem24.ll R600: Use optimized 24bit path in udivrem 2014-08-12 17:31:20 +00:00
udivrem64.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.ll R600/SI: Change formatting of printed FP immediates 2014-09-17 17:32:13 +00:00
unaligned-load-store.ll R600/SI: Fix broken check lines 2014-09-14 18:32:05 +00:00
unhandled-loop-condition-assertion.ll
unroll.ll
unsupported-cc.ll
urecip.ll
urem.ll
usubo.ll R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operations 2014-09-05 14:07:59 +00:00
v1i64-kernel-arg.ll
v_cndmask.ll
valu-i1.ll
vector-alloca.ll
vertex-fetch-encoding.ll
vop-shrink.ll R600/SI: Do abs/neg folding with ComplexPatterns 2014-08-01 00:32:39 +00:00
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll R600/SI: Implement areLoadsFromSameBasePtr 2014-08-06 00:29:43 +00:00
work-item-intrinsics.ll R600: Modernize work item intrinsics test 2014-07-31 22:11:03 +00:00
wrong-transalu-pos-fix.ll
xor.ll R600/SI: Enable selecting SALU inside branches 2014-09-24 01:33:28 +00:00
zero_extend.ll R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant 2014-08-11 22:18:17 +00:00

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.