Colin LeMahieu 3c159ed1a0 [Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228026 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-03 20:40:52 +00:00
..
intrinsics	[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.	2015-02-03 20:40:52 +00:00
absaddr-store.ll
absimm.ll
adde.ll
always-ext.ll
args.ll
ashift-left-right.ll
block-addr.ll	[Hexagon] Adding reg-reg indexed load forms.	2014-12-30 18:58:47 +00:00
BranchPredict.ll	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
cext-check.ll	[Hexagon] Reapplying 224775 load words.	2014-12-23 20:02:16 +00:00
cext-valid-packet1.ll
cext-valid-packet2.ll
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmpb_pred.ll
combine_ir.ll
combine.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll	Hexagon V5 FP Support.	2012-05-10 20:20:25 +00:00
ctlz-cttz-ctpop.ll
ctor.ll	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
dadd.ll	[Hexagon] Replacing old fadd/fsub instructions and updating references.	2015-01-15 16:30:07 +00:00
dmul.ll	[Hexagon] Deleting old float comparison instruction and updating references to new ones.	2015-01-15 17:28:14 +00:00
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll	[Hexagon] Replacing old fadd/fsub instructions and updating references.	2015-01-15 16:30:07 +00:00
dualstore.ll
extload-combine.ll	Hexagon: Add patterns to generate 'combine' instructions.	2013-05-14 17:16:38 +00:00
fadd.ll
fcmp.ll
float.ll
floatconvert-ieee-rnd-near.ll
fmul.ll
frame.ll
fsub.ll
fusedandshift.ll
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll
hwloop-cleanup.ll
hwloop-const.ll
hwloop-dbg.ll	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
hwloop-le.ll
hwloop-lt1.ll
hwloop-lt.ll
hwloop-ne.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll	[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.	2015-01-15 21:07:52 +00:00
indirect-br.ll
lit.local.cfg
macint.ll
memops1.ll
memops2.ll
memops3.ll
memops.ll
misaligned-access.ll
mpy.ll
newvaluejump2.ll
newvaluejump.ll
newvaluestore.ll	[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.	2014-12-29 20:44:51 +00:00
opt-fabs.ll
opt-fneg.ll
packetize_cond_inst.ll
postinc-load.ll
postinc-store.ll
pred-absolute-store.ll	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
remove_lsr.ll
simpletailcall.ll
split-const32-const64.ll
static.ll
struct_args_large.ll	[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.	2014-12-29 20:44:51 +00:00
struct_args.ll
sube.ll
tail-call-trunc.ll
tfr-to-combine.ll
union-1.ll
vaddh.ll
validate-offset.ll
zextloadi1.ll