llvm-6502/test/CodeGen/Thumb2
Evan Cheng 342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 01:34:54 +00:00
..
2009-07-17-CrossRegClassCopy.ll
2009-07-21-ISelBug.ll
2009-07-23-CPIslandBug.ll
2009-07-30-PEICrash.ll
2009-08-01-WrongLDRBOpc.ll
2009-08-02-CoalescerBug.ll
2009-08-04-CoalescerAssert.ll
2009-08-04-CoalescerBug.ll
2009-08-04-ScavengerAssert.ll
2009-08-04-SubregLoweringBug2.ll
2009-08-04-SubregLoweringBug3.ll
2009-08-04-SubregLoweringBug.ll
2009-08-06-SpDecBug.ll
2009-08-07-CoalescerBug.ll
2009-08-07-NeonFPBug.ll
2009-08-08-ScavengerAssert.ll
2009-08-10-ISelBug.ll
2009-08-21-PostRAKill4.ll
2009-09-01-PostRAProlog.ll
2009-09-28-ITBlockBug.ll
2009-10-15-ITBlockBranch.ll
2009-11-01-CopyReg2RegBug.ll
2009-11-11-ScavengerAssert.ll
2009-11-13-STRDBug.ll
2009-12-01-LoopIVUsers.ll Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 2011-08-30 01:34:54 +00:00
2010-01-06-TailDuplicateLabels.ll
2010-01-19-RemovePredicates.ll
2010-02-11-phi-cycle.ll
2010-02-24-BigStack.ll
2010-03-08-addi12-ccout.ll
2010-03-15-AsmCCClobber.ll
2010-04-15-DynAllocBug.ll
2010-04-26-CopyRegCrash.ll
2010-05-24-rsbs.ll
2010-06-14-NEONCoalescer.ll Fix more register allocation sensitive tests. 2011-07-08 00:24:06 +00:00
2010-06-19-ITBlockCrash.ll
2010-06-21-TailMergeBug.ll Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 2011-08-03 22:34:43 +00:00
2010-08-10-VarSizedAllocaBug.ll
2010-11-22-EpilogueBug.ll
2010-12-03-AddSPNarrowing.ll
2011-04-21-FILoweringBug.ll
2011-06-07-TwoAddrEarlyClobber.ll
bfi.ll
bfx.ll
buildvector-crash.ll
carry.ll
cortex-fp.ll
crash.ll
cross-rc-coalescing-1.ll
cross-rc-coalescing-2.ll
dg.exp
div.ll
frameless2.ll
frameless.ll
ifcvt-neon.ll
large-stack.ll
ldr-str-imm12.ll
lsr-deficiency.ll Fix more register allocation sensitive tests. 2011-07-08 00:24:06 +00:00
machine-licm.ll Make tBX_RET and tBX_RET_vararg predicable. 2011-07-08 21:50:04 +00:00
mul_const.ll
pic-load.ll
thumb2-adc.ll
thumb2-add2.ll
thumb2-add3.ll
thumb2-add4.ll
thumb2-add5.ll
thumb2-add6.ll
thumb2-add.ll FileCheck-ize another test. Reduces the llc invocations from 8 to 1, and 2011-07-02 21:34:52 +00:00
thumb2-and2.ll
thumb2-and.ll
thumb2-asr2.ll
thumb2-asr.ll
thumb2-barrier.ll
thumb2-bcc.ll Introduce MCCodeGenInfo, which keeps information that can affect codegen 2011-07-19 06:37:02 +00:00
thumb2-bfc.ll
thumb2-bic.ll
thumb2-branch.ll Improve test cases from r134746. 2011-07-12 16:06:01 +00:00
thumb2-call-tc.ll
thumb2-call.ll
thumb2-cbnz.ll
thumb2-clz.ll Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 2011-07-07 03:55:05 +00:00
thumb2-cmn2.ll
thumb2-cmn.ll
thumb2-cmp2.ll
thumb2-cmp.ll
thumb2-eor2.ll
thumb2-eor.ll
thumb2-ifcvt1-tc.ll
thumb2-ifcvt1.ll Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 2011-08-03 22:34:43 +00:00
thumb2-ifcvt2.ll
thumb2-ifcvt3.ll
thumb2-jtb.ll
thumb2-ldm.ll Thumb assembly parsing and encoding for LDM instruction. 2011-08-18 21:50:53 +00:00
thumb2-ldr_ext.ll
thumb2-ldr_post.ll
thumb2-ldr_pre.ll
thumb2-ldr.ll
thumb2-ldrb.ll
thumb2-ldrd.ll
thumb2-ldrh.ll
thumb2-lsl2.ll
thumb2-lsl.ll
thumb2-lsr2.ll
thumb2-lsr3.ll
thumb2-lsr.ll
thumb2-mla.ll
thumb2-mls.ll Update tests. 2011-08-19 22:19:48 +00:00
thumb2-mov.ll
thumb2-mul.ll Update tests. 2011-08-19 22:19:48 +00:00
thumb2-mulhi.ll
thumb2-mvn2.ll
thumb2-mvn.ll
thumb2-neg.ll
thumb2-orn2.ll
thumb2-orn.ll
thumb2-orr2.ll
thumb2-orr.ll
thumb2-pack.ll
thumb2-rev16.ll
thumb2-rev.ll Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 2011-07-07 03:55:05 +00:00
thumb2-ror.ll
thumb2-rsb2.ll
thumb2-rsb.ll
thumb2-sbc.ll
thumb2-select_xform.ll
thumb2-select.ll
thumb2-shifter.ll
thumb2-smla.ll
thumb2-smul.ll
thumb2-spill-q.ll
thumb2-str_post.ll
thumb2-str_pre.ll
thumb2-str.ll
thumb2-strb.ll
thumb2-strh.ll
thumb2-sub2.ll
thumb2-sub3.ll
thumb2-sub4.ll
thumb2-sub5.ll
thumb2-sub.ll
thumb2-sxt_rot.ll
thumb2-sxt-uxt.ll Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 2011-08-08 19:49:37 +00:00
thumb2-tbb.ll
thumb2-tbh.ll
thumb2-teq2.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-teq.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-tst2.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-tst.ll Improve codegen for select's: 2011-07-13 00:42:17 +00:00
thumb2-uxt_rot.ll
thumb2-uxtb.ll
tls1.ll
tls2.ll