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llvm-6502/lib/Target/Sparc
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Brian Gaeke 03203b423f update according to tonight's info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16866 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-09 05:58:27 +00:00
..
DelaySlotFiller.cpp Use TargetMachine::hasDelaySlot() instead of our old switch statement 2004-09-30 04:04:47 +00:00
FPMover.cpp Pass which converts FpMOVD (double move pseudoinstructions) to pairs 2004-09-29 03:24:34 +00:00
Makefile Fix file header path 2004-09-22 21:29:12 +00:00
README.txt update according to tonight's info 2004-10-09 05:58:27 +00:00
Sparc.h Add createSparcV8FPMoverPass(). 2004-09-29 03:25:39 +00:00
Sparc.td Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc 2004-09-22 20:09:29 +00:00
SparcAsmPrinter.cpp Don't use .quad to output double constants. The assembler must have a bug or 2004-09-29 19:59:06 +00:00
SparcInstrFormats.td Combine the F2 and F3 instruction classes into one file for simplicity 2004-09-22 21:38:42 +00:00
SparcInstrInfo.cpp Recognize FpMOVD as a move. 2004-09-29 16:45:47 +00:00
SparcInstrInfo.h I think that V8 should coallesce registers, don't you? 2004-07-25 06:19:04 +00:00
SparcInstrInfo.td Mark the instructions that have delay slots with the hasDelaySlot flag. 2004-09-30 04:04:48 +00:00
SparcRegisterInfo.cpp Use FpMOVD pseudo-instruction to move doubles around. 2004-09-29 03:27:30 +00:00
SparcRegisterInfo.h Code insertion methods now return void instead of an int. 2004-08-15 22:15:11 +00:00
SparcRegisterInfo.td SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned! 2004-09-27 18:22:18 +00:00
SparcTargetMachine.cpp Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 2004-10-09 05:57:01 +00:00
SparcTargetMachine.h Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 2004-10-09 05:57:01 +00:00
SparcV8CodeEmitter.cpp SparcV8 skeleton 2004-02-25 19:28:19 +00:00
SparcV8ISelSimple.cpp I think this will handle double args. 2004-09-30 19:44:32 +00:00
SparcV8JITInfo.h SparcV8 skeleton 2004-02-25 19:28:19 +00:00

README.txt 

SparcV8 backend skeleton
------------------------

This directory houses a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  It is not yet functionally complete.  Watch
this space for more news coming soon!

Current shootout results as of 28-Sept-2004
-------------------------------------------

Working: ackermann fib2 hash hello lists matrix methcall nestedloop
         sieve strcat random ary3 
Broken: heapsort (and objinst??)

To-do
-----

* support ADJCALLSTACK{UP,DOWN} pseudoinstrs around calls
* support calling functions with more than 6 args
* support 64-bit integer (long, ulong) arguments to functions
* support setcc on longs
* support basic binary operations on longs
* support casting <=32-bit integers, bools to long
* support casting 64-bit integers to FP types

$Date$