| .. |
|
AsmParser
|
MC: Clean up MCExpr naming. NFC.
|
2015-05-30 01:25:56 +00:00 |
|
InstPrinter
|
MC: Add target hook to control symbol quoting
|
2015-06-09 00:31:39 +00:00 |
|
MCTargetDesc
|
MC: Clean up the naming for MCMachObjectWriter. NFC.
|
2015-06-04 23:25:54 +00:00 |
|
TargetInfo
|
|
|
|
AMDGPU.h
|
Fix clang-cl self-host -Wc++11-narrowing bug
|
2015-06-08 21:57:57 +00:00 |
|
AMDGPU.td
|
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
|
2015-05-25 16:15:54 +00:00 |
|
AMDGPUAlwaysInlinePass.cpp
|
R600: Fix always inline pass breaking noinline functions
|
2015-04-22 17:10:44 +00:00 |
|
AMDGPUAsmPrinter.cpp
|
Move alignment from MCSectionData to MCSection.
|
2015-05-21 19:20:38 +00:00 |
|
AMDGPUAsmPrinter.h
|
R600/SI: Add some missing overrides
|
2015-04-08 02:07:05 +00:00 |
|
AMDGPUCallingConv.td
|
|
|
|
AMDGPUFrameLowering.cpp
|
[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
|
2015-05-05 17:38:16 +00:00 |
|
AMDGPUFrameLowering.h
|
[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
|
2015-05-05 17:38:16 +00:00 |
|
AMDGPUInstrInfo.cpp
|
[InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC
|
2015-06-08 20:09:58 +00:00 |
|
AMDGPUInstrInfo.h
|
[InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC
|
2015-06-08 20:09:58 +00:00 |
|
AMDGPUInstrInfo.td
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
AMDGPUInstructions.td
|
R600/SI: Remove explicit m0 operand from DS instructions
|
2015-05-12 15:00:49 +00:00 |
|
AMDGPUIntrinsicInfo.cpp
|
|
|
|
AMDGPUIntrinsicInfo.h
|
|
|
|
AMDGPUIntrinsics.td
|
|
|
|
AMDGPUISelDAGToDAG.cpp
|
R600/SI: Remove explicit m0 operand from DS instructions
|
2015-05-12 15:00:49 +00:00 |
|
AMDGPUISelLowering.cpp
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
AMDGPUISelLowering.h
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
AMDGPUMachineFunction.cpp
|
|
|
|
AMDGPUMachineFunction.h
|
|
|
|
AMDGPUMCInstLower.cpp
|
MC: Clean up MCExpr naming. NFC.
|
2015-05-30 01:25:56 +00:00 |
|
AMDGPUMCInstLower.h
|
|
|
|
AMDGPUPromoteAlloca.cpp
|
Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only
|
2015-05-18 22:13:54 +00:00 |
|
AMDGPURegisterInfo.cpp
|
|
|
|
AMDGPURegisterInfo.h
|
|
|
|
AMDGPURegisterInfo.td
|
|
|
|
AMDGPUSubtarget.cpp
|
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
|
2015-05-25 16:15:54 +00:00 |
|
AMDGPUSubtarget.h
|
R600: Re-enable sub-reg liveness
|
2015-06-04 01:20:04 +00:00 |
|
AMDGPUTargetMachine.cpp
|
R600/SI: add pass to mark CF live ranges as non-spillable
|
2015-05-12 17:13:02 +00:00 |
|
AMDGPUTargetMachine.h
|
|
|
|
AMDGPUTargetTransformInfo.cpp
|
[X86] Disable loop unrolling in loop vectorization pass when VF is 1.
|
2015-05-06 17:12:25 +00:00 |
|
AMDGPUTargetTransformInfo.h
|
[X86] Disable loop unrolling in loop vectorization pass when VF is 1.
|
2015-05-06 17:12:25 +00:00 |
|
AMDILCFGStructurizer.cpp
|
|
|
|
AMDKernelCodeT.h
|
|
|
|
CaymanInstructions.td
|
|
|
|
CIInstructions.td
|
R600/SI: Add assembler support for all CI and VI VOP1 instructions
|
2015-04-23 19:33:54 +00:00 |
|
CMakeLists.txt
|
R600/SI: add pass to mark CF live ranges as non-spillable
|
2015-05-12 17:13:02 +00:00 |
|
EvergreenInstructions.td
|
Reinstate revisions r234755, r234759, r234760
|
2015-04-30 17:15:56 +00:00 |
|
LLVMBuild.txt
|
|
|
|
Makefile
|
|
|
|
Processors.td
|
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
|
2015-05-25 16:15:54 +00:00 |
|
R600ClauseMergePass.cpp
|
|
|
|
R600ControlFlowFinalizer.cpp
|
|
|
|
R600Defines.h
|
|
|
|
R600EmitClauseMarkers.cpp
|
|
|
|
R600ExpandSpecialInstrs.cpp
|
|
|
|
R600InstrFormats.td
|
|
|
|
R600InstrInfo.cpp
|
|
|
|
R600InstrInfo.h
|
|
|
|
R600Instructions.td
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
R600Intrinsics.td
|
|
|
|
R600ISelLowering.cpp
|
R600: Rely on TypeLegalizer to use divrem instead of div/rem
|
2015-05-27 16:54:10 +00:00 |
|
R600ISelLowering.h
|
Reinstate revisions r234755, r234759, r234760
|
2015-04-30 17:15:56 +00:00 |
|
R600MachineFunctionInfo.cpp
|
|
|
|
R600MachineFunctionInfo.h
|
|
|
|
R600MachineScheduler.cpp
|
|
|
|
R600MachineScheduler.h
|
|
|
|
R600OptimizeVectorRegisters.cpp
|
|
|
|
R600Packetizer.cpp
|
|
|
|
R600RegisterInfo.cpp
|
|
|
|
R600RegisterInfo.h
|
|
|
|
R600RegisterInfo.td
|
|
|
|
R600Schedule.td
|
|
|
|
R600TextureIntrinsicsReplacer.cpp
|
Reduce dyn_cast<> to isa<> or cast<> where possible.
|
2015-04-10 11:24:51 +00:00 |
|
R700Instructions.td
|
|
|
|
SIAnnotateControlFlow.cpp
|
R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
|
2015-05-01 03:44:08 +00:00 |
|
SIDefines.h
|
R600/SI: Fix bug in VGPR spilling
|
2015-05-12 18:59:17 +00:00 |
|
SIFixControlFlowLiveIntervals.cpp
|
R600/SI: add pass to mark CF live ranges as non-spillable
|
2015-05-12 17:13:02 +00:00 |
|
SIFixSGPRCopies.cpp
|
R600/SI: Remove M0Reg register class
|
2015-05-12 15:00:52 +00:00 |
|
SIFixSGPRLiveRanges.cpp
|
|
|
|
SIFoldOperands.cpp
|
R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)
|
2015-05-12 14:18:11 +00:00 |
|
SIInsertWaits.cpp
|
|
|
|
SIInstrFormats.td
|
R600/SI: Fix bug in VGPR spilling
|
2015-05-12 18:59:17 +00:00 |
|
SIInstrInfo.cpp
|
R600/SI: Fix verifier error when producing v_madmk_f32
|
2015-04-24 01:57:58 +00:00 |
|
SIInstrInfo.h
|
R600/SI: Fix bug in VGPR spilling
|
2015-05-12 18:59:17 +00:00 |
|
SIInstrInfo.td
|
R600/SI: Add assembler support for all CI and VI VOP2 instructions
|
2015-05-26 15:55:52 +00:00 |
|
SIInstructions.td
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
SIIntrinsics.td
|
|
|
|
SIISelLowering.cpp
|
R600: Switch to using generic min / max nodes.
|
2015-06-09 00:52:37 +00:00 |
|
SIISelLowering.h
|
Add address space argument to isLegalAddressingMode
|
2015-06-01 05:31:59 +00:00 |
|
SILoadStoreOptimizer.cpp
|
R600/SI: Remove explicit m0 operand from DS instructions
|
2015-05-12 15:00:49 +00:00 |
|
SILowerControlFlow.cpp
|
R600/SI: Fix indirect addressing with a negative constant offset
|
2015-04-23 20:32:01 +00:00 |
|
SILowerI1Copies.cpp
|
|
|
|
SIMachineFunctionInfo.cpp
|
|
|
|
SIMachineFunctionInfo.h
|
|
|
|
SIPrepareScratchRegs.cpp
|
R600/SI: Fix bug in VGPR spilling
|
2015-05-12 18:59:17 +00:00 |
|
SIRegisterInfo.cpp
|
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0
|
2015-05-12 15:00:53 +00:00 |
|
SIRegisterInfo.h
|
|
|
|
SIRegisterInfo.td
|
R600/SI: Remove M0Reg register class
|
2015-05-12 15:00:52 +00:00 |
|
SISchedule.td
|
|
|
|
SIShrinkInstructions.cpp
|
|
|
|
SITypeRewriter.cpp
|
|
|
|
VIInstrFormats.td
|
|
|
|
VIInstructions.td
|
R600/SI: Add assembler support for all CI and VI VOP2 instructions
|
2015-05-26 15:55:52 +00:00 |
