llvm-6502/lib/CodeGen
2009-11-16 18:08:46 +00:00
..
AsmPrinter Support spill comments. 2009-11-16 15:12:23 +00:00
PBQP
SelectionDAG Enable the tail call optimization when the caller returns undef. 2009-11-14 02:06:30 +00:00
AggressiveAntiDepBreaker.cpp Allow target to specify regclass for which antideps will only be broken along the critical path. 2009-11-13 19:52:48 +00:00
AggressiveAntiDepBreaker.h Allow target to specify regclass for which antideps will only be broken along the critical path. 2009-11-13 19:52:48 +00:00
AntiDepBreaker.h Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 2009-11-03 20:57:50 +00:00
BranchFolding.cpp Whitespace: be consistent with pointer syntax. 2009-11-16 18:08:46 +00:00
BranchFolding.h Make the BranchFolderPass class local to BranchFolding.cpp. 2009-11-12 01:59:26 +00:00
CMakeLists.txt Fix CMake makefiles 2009-11-04 01:32:06 +00:00
CodePlacementOpt.cpp Move the utility function UpdateTerminator() from CodePlacementOpt() into 2009-11-12 03:55:33 +00:00
CriticalAntiDepBreaker.cpp Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 2009-11-03 20:57:50 +00:00
CriticalAntiDepBreaker.h Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 2009-11-03 20:57:50 +00:00
DeadMachineInstructionElim.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
DwarfEHPrepare.cpp Don't put in these EH changes. 2009-10-29 00:37:35 +00:00
ELF.h Move DataTypes.h to include/llvm/System, update all users. This breaks the last 2009-10-26 01:35:46 +00:00
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp
ELFWriter.h
ExactHazardRecognizer.cpp Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. 2009-11-03 20:57:50 +00:00
ExactHazardRecognizer.h
GCMetadata.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
IfConversion.cpp Revert r85346 change to control tail merging by CodeGenOpt::Level. 2009-10-28 20:46:46 +00:00
IntrinsicLowering.cpp Codegen support for the llvm.invariant/lifetime.start/end intrinsics: 2009-11-10 09:08:09 +00:00
LatencyPriorityQueue.cpp Rename registers to break output dependencies in addition to anti-dependencies. 2009-11-12 19:08:21 +00:00
LiveInterval.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
LiveIntervalAnalysis.cpp Hide a couple of options. 2009-11-09 06:49:37 +00:00
LiveStackAnalysis.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
LiveVariables.cpp Fix PR5410: LiveVariables lost subreg def: 2009-11-13 20:36:40 +00:00
LLVMTargetMachine.cpp Now that code placement optimization pass is run for JIT, make sure it's before pre-emit passes. 2009-11-05 01:16:59 +00:00
LowerSubregs.cpp Code clean up. 2009-10-25 07:49:57 +00:00
MachineBasicBlock.cpp Move the utility function UpdateTerminator() from CodePlacementOpt() into 2009-11-12 03:55:33 +00:00
MachineDominators.cpp
MachineFunction.cpp Do not merge jump tables this early. Branch folding will do any necessary 2009-11-14 20:15:03 +00:00
MachineFunctionAnalysis.cpp Constify MachineFunctionAnalysis' TargetMachine reference. 2009-11-09 18:18:49 +00:00
MachineFunctionPass.cpp
MachineInstr.cpp Print "..." instead of all the uninteresting register clobbers on call 2009-11-09 19:38:45 +00:00
MachineLICM.cpp - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 2009-11-07 03:52:02 +00:00
MachineLoopInfo.cpp Add getTopBlock and getBottomBlock member functions to MachineLoopInfo. 2009-10-20 04:16:37 +00:00
MachineModuleInfo.cpp "Attach debug info with llvm instructions" mode was enabled a month ago. Now make it permanent and remove old way of inserting intrinsics to encode debug info for line number and scopes. 2009-11-12 19:02:56 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
MachineVerifier.cpp Add MachineFunction::verify() to call the machine code verifier directly. 2009-11-13 21:56:09 +00:00
MachO.h
MachOCodeEmitter.cpp
MachOCodeEmitter.h
MachOWriter.cpp
MachOWriter.h
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
Passes.cpp
PHIElimination.cpp Fix for the original bug in PR5495 - Look at uses as well as defs when determining the PHI-copy insert point. 2009-11-16 02:00:09 +00:00
PHIElimination.h Fix PHIElimination optimization that uses MBB->getBasicBlock. 2009-11-13 21:56:15 +00:00
PostRASchedulerList.cpp Allow target to specify regclass for which antideps will only be broken along the critical path. 2009-11-13 19:52:48 +00:00
PreAllocSplitting.cpp - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 2009-11-14 02:55:43 +00:00
ProcessImplicitDefs.cpp For some targets, a copy can use a register multiple times, e.g. ppc. 2009-11-16 05:52:06 +00:00
PrologEpilogInserter.cpp Add a bool flag to StackObjects telling whether they reference spill 2009-11-12 20:49:22 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Do some cleanups suggested by Chris. 2009-11-12 21:49:55 +00:00
README.txt
RegAllocLinearScan.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
RegAllocLocal.cpp Add a bool flag to StackObjects telling whether they reference spill 2009-11-12 20:49:22 +00:00
RegAllocPBQP.cpp Added an assert to the PBQP allocator to catch infinite cost solutions which might otherwise lead to miscompilations. 2009-11-15 04:39:51 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp RegScavenger::enterBasicBlock should always reset register state. 2009-11-12 07:49:10 +00:00
ScheduleDAG.cpp Rename registers to break output dependencies in addition to anti-dependencies. 2009-11-12 19:08:21 +00:00
ScheduleDAGEmit.cpp Add assertion checks here to turn silent miscompiles into aborts. 2009-10-30 23:59:06 +00:00
ScheduleDAGInstrs.cpp Fix dependencies added to model memory aliasing for post-RA scheduling. The dependencies were overly conservative for memory access that are known not to alias. 2009-11-09 19:22:17 +00:00
ScheduleDAGInstrs.h Spill slots cannot alias. 2009-10-18 19:58:47 +00:00
ScheduleDAGPrinter.cpp Trim unnecessary includes. 2009-10-20 04:23:20 +00:00
ShadowStackGC.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 2009-11-14 02:55:43 +00:00
SimpleRegisterCoalescing.h The Indexes Patch. 2009-11-03 23:52:08 +00:00
SjLjEHPrepare.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
SlotIndexes.cpp Added an API to the SlotIndexes pass to allow new instructions to be inserted into the numbering. 2009-11-14 00:02:51 +00:00
Spiller.cpp Added an API to the SlotIndexes pass to allow new instructions to be inserted into the numbering. 2009-11-14 00:02:51 +00:00
Spiller.h
StackProtector.cpp Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 2009-10-25 06:33:48 +00:00
StackSlotColoring.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
StrongPHIElimination.cpp The Indexes Patch. 2009-11-03 23:52:08 +00:00
TargetInstrInfoImpl.cpp Check if subreg index is zero. 2009-11-16 06:31:49 +00:00
TwoAddressInstructionPass.cpp - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 2009-11-14 02:55:43 +00:00
UnreachableBlockElim.cpp Remove includes of Support/Compiler.h that are no longer needed after the 2009-10-25 06:57:41 +00:00
VirtRegMap.cpp Add a bool flag to StackObjects telling whether they reference spill 2009-11-12 20:49:22 +00:00
VirtRegMap.h The Indexes Patch. 2009-11-03 23:52:08 +00:00
VirtRegRewriter.cpp Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter. 2009-11-14 03:42:17 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.